Clean up trailing whitespace in the kernel headers.
And fix the scripts so they stop letting trailing whitespace through.
Change-Id: Ie109fbe1f63321e565ba0fa60fee8e9cf3a61cfc
diff --git a/libc/kernel/arch-mips/asm/sn/ioc3.h b/libc/kernel/arch-mips/asm/sn/ioc3.h
index 9771304..46ba4dd 100644
--- a/libc/kernel/arch-mips/asm/sn/ioc3.h
+++ b/libc/kernel/arch-mips/asm/sn/ioc3.h
@@ -193,21 +193,21 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ERXBUF_BYTECNT_SHIFT 16
#define ERXBUF_V 0x80000000
-#define ERXBUF_CRCERR 0x00000001
-#define ERXBUF_FRAMERR 0x00000002
+#define ERXBUF_CRCERR 0x00000001
+#define ERXBUF_FRAMERR 0x00000002
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define ERXBUF_CODERR 0x00000004
-#define ERXBUF_INVPREAMB 0x00000008
-#define ERXBUF_LOLEN 0x00007000
-#define ERXBUF_HILEN 0x03ff0000
+#define ERXBUF_CODERR 0x00000004
+#define ERXBUF_INVPREAMB 0x00000008
+#define ERXBUF_LOLEN 0x00007000
+#define ERXBUF_HILEN 0x03ff0000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define ERXBUF_MULTICAST 0x04000000
-#define ERXBUF_BROADCAST 0x08000000
-#define ERXBUF_LONGEVENT 0x10000000
-#define ERXBUF_BADPKT 0x20000000
+#define ERXBUF_MULTICAST 0x04000000
+#define ERXBUF_BROADCAST 0x08000000
+#define ERXBUF_LONGEVENT 0x10000000
+#define ERXBUF_BADPKT 0x20000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define ERXBUF_GOODPKT 0x40000000
-#define ERXBUF_CARRIER 0x80000000
+#define ERXBUF_GOODPKT 0x40000000
+#define ERXBUF_CARRIER 0x80000000
#define ETXD_DATALEN 104
struct ioc3_etxd {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@@ -218,15 +218,15 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u8 data[ETXD_DATALEN];
};
-#define ETXD_BYTECNT_MASK 0x000007ff
-#define ETXD_INTWHENDONE 0x00001000
+#define ETXD_BYTECNT_MASK 0x000007ff
+#define ETXD_INTWHENDONE 0x00001000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define ETXD_D0V 0x00010000
-#define ETXD_B1V 0x00020000
-#define ETXD_B2V 0x00040000
-#define ETXD_DOCHECKSUM 0x00080000
+#define ETXD_D0V 0x00010000
+#define ETXD_B1V 0x00020000
+#define ETXD_B2V 0x00040000
+#define ETXD_DOCHECKSUM 0x00080000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define ETXD_CHKOFF_MASK 0x07f00000
+#define ETXD_CHKOFF_MASK 0x07f00000
#define ETXD_CHKOFF_SHIFT 20
#define ETXD_D0CNT_MASK 0x0000007f
#define ETXD_B1CNT_MASK 0x0007ff00
@@ -241,22 +241,22 @@
#define IOC3_BYTEBUS_DEV3 0xe0000L
#define IOC3_SIO_BASE 0x20000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IOC3_SIO_UARTC (IOC3_SIO_BASE+0x141)
-#define IOC3_SIO_KBDCG (IOC3_SIO_BASE+0x142)
-#define IOC3_SIO_PP_BASE (IOC3_SIO_BASE+PP_BASE)
-#define IOC3_SIO_RTC_BASE (IOC3_SIO_BASE+0x168)
+#define IOC3_SIO_UARTC (IOC3_SIO_BASE+0x141)
+#define IOC3_SIO_KBDCG (IOC3_SIO_BASE+0x142)
+#define IOC3_SIO_PP_BASE (IOC3_SIO_BASE+PP_BASE)
+#define IOC3_SIO_RTC_BASE (IOC3_SIO_BASE+0x168)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IOC3_SIO_UB_BASE (IOC3_SIO_BASE+UARTB_BASE)
-#define IOC3_SIO_UA_BASE (IOC3_SIO_BASE+UARTA_BASE)
-#define IOC3_SSRAM IOC3_RAM_OFF
-#define IOC3_SSRAM_LEN 0x40000
+#define IOC3_SIO_UB_BASE (IOC3_SIO_BASE+UARTB_BASE)
+#define IOC3_SIO_UA_BASE (IOC3_SIO_BASE+UARTA_BASE)
+#define IOC3_SSRAM IOC3_RAM_OFF
+#define IOC3_SSRAM_LEN 0x40000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IOC3_SSRAM_DM 0x0000ffff
-#define IOC3_SSRAM_PM 0x00010000
-#define PCI_SCR_PAR_RESP_EN 0x00000040
-#define PCI_SCR_SERR_EN 0x00000100
+#define IOC3_SSRAM_DM 0x0000ffff
+#define IOC3_SSRAM_PM 0x00010000
+#define PCI_SCR_PAR_RESP_EN 0x00000040
+#define PCI_SCR_SERR_EN 0x00000100
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PCI_SCR_DROP_MODE_EN 0x00008000
+#define PCI_SCR_DROP_MODE_EN 0x00008000
#define PCI_SCR_RX_SERR (0x1 << 16)
#define PCI_SCR_DROP_MODE (0x1 << 17)
#define PCI_SCR_SIG_PAR_ERR (0x1 << 24)
@@ -267,158 +267,158 @@
#define PCI_SCR_SIG_SERR (0x1 << 30)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PCI_SCR_PAR_ERR (0x1 << 31)
-#define KM_CSR_K_WRT_PEND 0x00000001
-#define KM_CSR_M_WRT_PEND 0x00000002
-#define KM_CSR_K_LCB 0x00000004
+#define KM_CSR_K_WRT_PEND 0x00000001
+#define KM_CSR_M_WRT_PEND 0x00000002
+#define KM_CSR_K_LCB 0x00000004
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define KM_CSR_M_LCB 0x00000008
-#define KM_CSR_K_DATA 0x00000010
-#define KM_CSR_K_CLK 0x00000020
-#define KM_CSR_K_PULL_DATA 0x00000040
+#define KM_CSR_M_LCB 0x00000008
+#define KM_CSR_K_DATA 0x00000010
+#define KM_CSR_K_CLK 0x00000020
+#define KM_CSR_K_PULL_DATA 0x00000040
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define KM_CSR_K_PULL_CLK 0x00000080
-#define KM_CSR_M_DATA 0x00000100
-#define KM_CSR_M_CLK 0x00000200
-#define KM_CSR_M_PULL_DATA 0x00000400
+#define KM_CSR_K_PULL_CLK 0x00000080
+#define KM_CSR_M_DATA 0x00000100
+#define KM_CSR_M_CLK 0x00000200
+#define KM_CSR_M_PULL_DATA 0x00000400
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define KM_CSR_M_PULL_CLK 0x00000800
-#define KM_CSR_EMM_MODE 0x00001000
-#define KM_CSR_SIM_MODE 0x00002000
-#define KM_CSR_K_SM_IDLE 0x00004000
+#define KM_CSR_M_PULL_CLK 0x00000800
+#define KM_CSR_EMM_MODE 0x00001000
+#define KM_CSR_SIM_MODE 0x00002000
+#define KM_CSR_K_SM_IDLE 0x00004000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define KM_CSR_M_SM_IDLE 0x00008000
-#define KM_CSR_K_TO 0x00010000
-#define KM_CSR_M_TO 0x00020000
-#define KM_CSR_K_TO_EN 0x00040000
+#define KM_CSR_M_SM_IDLE 0x00008000
+#define KM_CSR_K_TO 0x00010000
+#define KM_CSR_M_TO 0x00020000
+#define KM_CSR_K_TO_EN 0x00040000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define KM_CSR_M_TO_EN 0x00080000
-#define KM_CSR_K_CLAMP_ONE 0x00100000
-#define KM_CSR_M_CLAMP_ONE 0x00200000
-#define KM_CSR_K_CLAMP_THREE 0x00400000
+#define KM_CSR_M_TO_EN 0x00080000
+#define KM_CSR_K_CLAMP_ONE 0x00100000
+#define KM_CSR_M_CLAMP_ONE 0x00200000
+#define KM_CSR_K_CLAMP_THREE 0x00400000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define KM_CSR_M_CLAMP_THREE 0x00800000
-#define KM_RD_DATA_2 0x000000ff
+#define KM_CSR_M_CLAMP_THREE 0x00800000
+#define KM_RD_DATA_2 0x000000ff
#define KM_RD_DATA_2_SHIFT 0
-#define KM_RD_DATA_1 0x0000ff00
+#define KM_RD_DATA_1 0x0000ff00
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KM_RD_DATA_1_SHIFT 8
-#define KM_RD_DATA_0 0x00ff0000
+#define KM_RD_DATA_0 0x00ff0000
#define KM_RD_DATA_0_SHIFT 16
-#define KM_RD_FRAME_ERR_2 0x01000000
+#define KM_RD_FRAME_ERR_2 0x01000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define KM_RD_FRAME_ERR_1 0x02000000
-#define KM_RD_FRAME_ERR_0 0x04000000
-#define KM_RD_KBD_MSE 0x08000000
-#define KM_RD_OFLO 0x10000000
+#define KM_RD_FRAME_ERR_1 0x02000000
+#define KM_RD_FRAME_ERR_0 0x04000000
+#define KM_RD_KBD_MSE 0x08000000
+#define KM_RD_OFLO 0x10000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define KM_RD_VALID_2 0x20000000
-#define KM_RD_VALID_1 0x40000000
-#define KM_RD_VALID_0 0x80000000
+#define KM_RD_VALID_2 0x20000000
+#define KM_RD_VALID_1 0x40000000
+#define KM_RD_VALID_0 0x80000000
#define KM_RD_VALID_ALL (KM_RD_VALID_0|KM_RD_VALID_1|KM_RD_VALID_2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define KM_WD_WRT_DATA 0x000000ff
+#define KM_WD_WRT_DATA 0x000000ff
#define KM_WD_WRT_DATA_SHIFT 0
-#define RXSB_OVERRUN 0x01
-#define RXSB_PAR_ERR 0x02
+#define RXSB_OVERRUN 0x01
+#define RXSB_PAR_ERR 0x02
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define RXSB_FRAME_ERR 0x04
-#define RXSB_BREAK 0x08
-#define RXSB_CTS 0x10
-#define RXSB_DCD 0x20
+#define RXSB_FRAME_ERR 0x04
+#define RXSB_BREAK 0x08
+#define RXSB_CTS 0x10
+#define RXSB_DCD 0x20
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define RXSB_MODEM_VALID 0x40
-#define RXSB_DATA_VALID 0x80
-#define TXCB_INT_WHEN_DONE 0x20
-#define TXCB_INVALID 0x00
+#define RXSB_MODEM_VALID 0x40
+#define RXSB_DATA_VALID 0x80
+#define TXCB_INT_WHEN_DONE 0x20
+#define TXCB_INVALID 0x00
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define TXCB_VALID 0x40
-#define TXCB_MCR 0x80
-#define TXCB_DELAY 0xc0
-#define SBBR_L_SIZE 0x00000001
+#define TXCB_VALID 0x40
+#define TXCB_MCR 0x80
+#define TXCB_DELAY 0xc0
+#define SBBR_L_SIZE 0x00000001
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SBBR_L_BASE 0xfffff000
-#define SSCR_RX_THRESHOLD 0x000001ff
-#define SSCR_TX_TIMER_BUSY 0x00010000
-#define SSCR_HFC_EN 0x00020000
+#define SBBR_L_BASE 0xfffff000
+#define SSCR_RX_THRESHOLD 0x000001ff
+#define SSCR_TX_TIMER_BUSY 0x00010000
+#define SSCR_HFC_EN 0x00020000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SSCR_RX_RING_DCD 0x00040000
-#define SSCR_RX_RING_CTS 0x00080000
-#define SSCR_HIGH_SPD 0x00100000
-#define SSCR_DIAG 0x00200000
+#define SSCR_RX_RING_DCD 0x00040000
+#define SSCR_RX_RING_CTS 0x00080000
+#define SSCR_HIGH_SPD 0x00100000
+#define SSCR_DIAG 0x00200000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SSCR_RX_DRAIN 0x08000000
-#define SSCR_DMA_EN 0x10000000
-#define SSCR_DMA_PAUSE 0x20000000
-#define SSCR_PAUSE_STATE 0x40000000
+#define SSCR_RX_DRAIN 0x08000000
+#define SSCR_DMA_EN 0x10000000
+#define SSCR_DMA_PAUSE 0x20000000
+#define SSCR_PAUSE_STATE 0x40000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SSCR_RESET 0x80000000
-#define PROD_CONS_PTR_4K 0x00000ff8
-#define PROD_CONS_PTR_1K 0x000003f8
+#define SSCR_RESET 0x80000000
+#define PROD_CONS_PTR_4K 0x00000ff8
+#define PROD_CONS_PTR_1K 0x000003f8
#define PROD_CONS_PTR_OFF 3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SRCIR_ARM 0x80000000
-#define SRPIR_BYTE_CNT 0x07000000
+#define SRCIR_ARM 0x80000000
+#define SRPIR_BYTE_CNT 0x07000000
#define SRPIR_BYTE_CNT_SHIFT 24
-#define STCIR_BYTE_CNT 0x0f000000
+#define STCIR_BYTE_CNT 0x0f000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define STCIR_BYTE_CNT_SHIFT 24
-#define SHADOW_DR 0x00000001
-#define SHADOW_OE 0x00000002
-#define SHADOW_PE 0x00000004
+#define SHADOW_DR 0x00000001
+#define SHADOW_OE 0x00000002
+#define SHADOW_PE 0x00000004
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SHADOW_FE 0x00000008
-#define SHADOW_BI 0x00000010
-#define SHADOW_THRE 0x00000020
-#define SHADOW_TEMT 0x00000040
+#define SHADOW_FE 0x00000008
+#define SHADOW_BI 0x00000010
+#define SHADOW_THRE 0x00000020
+#define SHADOW_TEMT 0x00000040
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SHADOW_RFCE 0x00000080
-#define SHADOW_DCTS 0x00010000
-#define SHADOW_DDCD 0x00080000
-#define SHADOW_CTS 0x00100000
+#define SHADOW_RFCE 0x00000080
+#define SHADOW_DCTS 0x00010000
+#define SHADOW_DDCD 0x00080000
+#define SHADOW_CTS 0x00100000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SHADOW_DCD 0x00800000
-#define SHADOW_DTR 0x01000000
-#define SHADOW_RTS 0x02000000
-#define SHADOW_OUT1 0x04000000
+#define SHADOW_DCD 0x00800000
+#define SHADOW_DTR 0x01000000
+#define SHADOW_RTS 0x02000000
+#define SHADOW_OUT1 0x04000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SHADOW_OUT2 0x08000000
-#define SHADOW_LOOP 0x10000000
-#define SRTR_CNT 0x00000fff
-#define SRTR_CNT_VAL 0x0fff0000
+#define SHADOW_OUT2 0x08000000
+#define SHADOW_LOOP 0x10000000
+#define SRTR_CNT 0x00000fff
+#define SRTR_CNT_VAL 0x0fff0000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SRTR_CNT_VAL_SHIFT 16
-#define SRTR_HZ 16000
-#define SIO_IR_SA_TX_MT 0x00000001
-#define SIO_IR_SA_RX_FULL 0x00000002
+#define SRTR_HZ 16000
+#define SIO_IR_SA_TX_MT 0x00000001
+#define SIO_IR_SA_RX_FULL 0x00000002
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SIO_IR_SA_RX_HIGH 0x00000004
-#define SIO_IR_SA_RX_TIMER 0x00000008
-#define SIO_IR_SA_DELTA_DCD 0x00000010
-#define SIO_IR_SA_DELTA_CTS 0x00000020
+#define SIO_IR_SA_RX_HIGH 0x00000004
+#define SIO_IR_SA_RX_TIMER 0x00000008
+#define SIO_IR_SA_DELTA_DCD 0x00000010
+#define SIO_IR_SA_DELTA_CTS 0x00000020
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SIO_IR_SA_INT 0x00000040
-#define SIO_IR_SA_TX_EXPLICIT 0x00000080
-#define SIO_IR_SA_MEMERR 0x00000100
-#define SIO_IR_SB_TX_MT 0x00000200
+#define SIO_IR_SA_INT 0x00000040
+#define SIO_IR_SA_TX_EXPLICIT 0x00000080
+#define SIO_IR_SA_MEMERR 0x00000100
+#define SIO_IR_SB_TX_MT 0x00000200
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SIO_IR_SB_RX_FULL 0x00000400
-#define SIO_IR_SB_RX_HIGH 0x00000800
-#define SIO_IR_SB_RX_TIMER 0x00001000
-#define SIO_IR_SB_DELTA_DCD 0x00002000
+#define SIO_IR_SB_RX_FULL 0x00000400
+#define SIO_IR_SB_RX_HIGH 0x00000800
+#define SIO_IR_SB_RX_TIMER 0x00001000
+#define SIO_IR_SB_DELTA_DCD 0x00002000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SIO_IR_SB_DELTA_CTS 0x00004000
-#define SIO_IR_SB_INT 0x00008000
-#define SIO_IR_SB_TX_EXPLICIT 0x00010000
-#define SIO_IR_SB_MEMERR 0x00020000
+#define SIO_IR_SB_DELTA_CTS 0x00004000
+#define SIO_IR_SB_INT 0x00008000
+#define SIO_IR_SB_TX_EXPLICIT 0x00010000
+#define SIO_IR_SB_MEMERR 0x00020000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SIO_IR_PP_INT 0x00040000
-#define SIO_IR_PP_INTA 0x00080000
-#define SIO_IR_PP_INTB 0x00100000
-#define SIO_IR_PP_MEMERR 0x00200000
+#define SIO_IR_PP_INT 0x00040000
+#define SIO_IR_PP_INTA 0x00080000
+#define SIO_IR_PP_INTB 0x00100000
+#define SIO_IR_PP_MEMERR 0x00200000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SIO_IR_KBD_INT 0x00400000
-#define SIO_IR_RT_INT 0x08000000
-#define SIO_IR_GEN_INT1 0x10000000
+#define SIO_IR_KBD_INT 0x00400000
+#define SIO_IR_RT_INT 0x08000000
+#define SIO_IR_GEN_INT1 0x10000000
#define SIO_IR_GEN_INT_SHIFT 28
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SIO_IR_SA (SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL | SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER | SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS | SIO_IR_SA_INT | SIO_IR_SA_TX_EXPLICIT | SIO_IR_SA_MEMERR)
@@ -427,61 +427,61 @@
#define SIO_IR_RT (SIO_IR_RT_INT | SIO_IR_GEN_INT1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IOC3_PENDING_INTRS(mem) (PCI_INW(&((mem)->sio_ir)) & PCI_INW(&((mem)->sio_ies_ro)))
-#define SIO_CR_SIO_RESET 0x00000001
-#define SIO_CR_SER_A_BASE 0x000000fe
+#define SIO_CR_SIO_RESET 0x00000001
+#define SIO_CR_SER_A_BASE 0x000000fe
#define SIO_CR_SER_A_BASE_SHIFT 1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SIO_CR_SER_B_BASE 0x00007f00
+#define SIO_CR_SER_B_BASE 0x00007f00
#define SIO_CR_SER_B_BASE_SHIFT 8
-#define SIO_SR_CMD_PULSE 0x00078000
+#define SIO_SR_CMD_PULSE 0x00078000
#define SIO_CR_CMD_PULSE_SHIFT 15
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SIO_CR_ARB_DIAG 0x00380000
+#define SIO_CR_ARB_DIAG 0x00380000
#define SIO_CR_ARB_DIAG_TXA 0x00000000
#define SIO_CR_ARB_DIAG_RXA 0x00080000
#define SIO_CR_ARB_DIAG_TXB 0x00100000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SIO_CR_ARB_DIAG_RXB 0x00180000
#define SIO_CR_ARB_DIAG_PP 0x00200000
-#define SIO_CR_ARB_DIAG_IDLE 0x00400000
-#define INT_OUT_COUNT 0x0000ffff
+#define SIO_CR_ARB_DIAG_IDLE 0x00400000
+#define INT_OUT_COUNT 0x0000ffff
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define INT_OUT_MODE 0x00070000
-#define INT_OUT_MODE_0 0x00000000
-#define INT_OUT_MODE_1 0x00040000
-#define INT_OUT_MODE_1PULSE 0x00050000
+#define INT_OUT_MODE 0x00070000
+#define INT_OUT_MODE_0 0x00000000
+#define INT_OUT_MODE_1 0x00040000
+#define INT_OUT_MODE_1PULSE 0x00050000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define INT_OUT_MODE_PULSES 0x00060000
-#define INT_OUT_MODE_SQW 0x00070000
-#define INT_OUT_DIAG 0x40000000
-#define INT_OUT_INT_OUT 0x80000000
+#define INT_OUT_MODE_PULSES 0x00060000
+#define INT_OUT_MODE_SQW 0x00070000
+#define INT_OUT_DIAG 0x40000000
+#define INT_OUT_INT_OUT 0x80000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define INT_OUT_NS_PER_TICK (30 * 260)
-#define INT_OUT_TICKS_PER_PULSE 3
+#define INT_OUT_NS_PER_TICK (30 * 260)
+#define INT_OUT_TICKS_PER_PULSE 3
#define INT_OUT_US_TO_COUNT(x) (((x) * 10 + INT_OUT_NS_PER_TICK / 200) * 100 / INT_OUT_NS_PER_TICK - 1)
#define INT_OUT_COUNT_TO_US(x) (((x) + 1) * INT_OUT_NS_PER_TICK / 1000)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define INT_OUT_MIN_TICKS 3
-#define INT_OUT_MAX_TICKS INT_OUT_COUNT
-#define GPCR_DIR 0x000000ff
-#define GPCR_DIR_PIN(x) (1<<(x))
+#define INT_OUT_MIN_TICKS 3
+#define INT_OUT_MAX_TICKS INT_OUT_COUNT
+#define GPCR_DIR 0x000000ff
+#define GPCR_DIR_PIN(x) (1<<(x))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define GPCR_EDGE 0x000f0000
-#define GPCR_EDGE_PIN(x) (1<<((x)+15))
-#define GPCR_INT_OUT_EN 0x00100000
-#define GPCR_MLAN_EN 0x00200000
+#define GPCR_EDGE 0x000f0000
+#define GPCR_EDGE_PIN(x) (1<<((x)+15))
+#define GPCR_INT_OUT_EN 0x00100000
+#define GPCR_MLAN_EN 0x00200000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define GPCR_DIR_SERA_XCVR 0x00000080
-#define GPCR_DIR_SERB_XCVR 0x00000040
-#define GPCR_DIR_PHY_RST 0x00000020
-#define GPCR_PHY_RESET 0x20
+#define GPCR_DIR_SERA_XCVR 0x00000080
+#define GPCR_DIR_SERB_XCVR 0x00000040
+#define GPCR_DIR_PHY_RST 0x00000020
+#define GPCR_PHY_RESET 0x20
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define GPCR_UARTB_MODESEL 0x40
-#define GPCR_UARTA_MODESEL 0x80
-#define GPPR_PHY_RESET_PIN 5
-#define GPPR_UARTB_MODESEL_PIN 6
+#define GPCR_UARTB_MODESEL 0x40
+#define GPCR_UARTA_MODESEL 0x80
+#define GPPR_PHY_RESET_PIN 5
+#define GPPR_UARTB_MODESEL_PIN 6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define GPPR_UARTA_MODESEL_PIN 7
+#define GPPR_UARTA_MODESEL_PIN 7
#define EMCR_DUPLEX 0x00000001
#define EMCR_PROMISC 0x00000002
#define EMCR_PADEN 0x00000004
@@ -523,10 +523,10 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EISR_TXMEMERR 0x02000000
#define EISR_TXPARERR 0x04000000
-#define ERCSR_THRESH_MASK 0x000001ff
-#define ERCSR_RX_TMR 0x40000000
+#define ERCSR_THRESH_MASK 0x000001ff
+#define ERCSR_RX_TMR 0x40000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define ERCSR_DIAG_OFLO 0x80000000
+#define ERCSR_DIAG_OFLO 0x80000000
#define ERBR_ALIGNMENT 4096
#define ERBR_L_RXRINGBASE_MASK 0xfffff000
#define ERBAR_BARRIER_BIT 0x0100
@@ -581,29 +581,29 @@
#define ERXBUF_BYTECNT_SHIFT 16
#define ERXBUF_V 0x80000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define ERXBUF_CRCERR 0x00000001
-#define ERXBUF_FRAMERR 0x00000002
-#define ERXBUF_CODERR 0x00000004
-#define ERXBUF_INVPREAMB 0x00000008
+#define ERXBUF_CRCERR 0x00000001
+#define ERXBUF_FRAMERR 0x00000002
+#define ERXBUF_CODERR 0x00000004
+#define ERXBUF_INVPREAMB 0x00000008
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define ERXBUF_LOLEN 0x00007000
-#define ERXBUF_HILEN 0x03ff0000
-#define ERXBUF_MULTICAST 0x04000000
-#define ERXBUF_BROADCAST 0x08000000
+#define ERXBUF_LOLEN 0x00007000
+#define ERXBUF_HILEN 0x03ff0000
+#define ERXBUF_MULTICAST 0x04000000
+#define ERXBUF_BROADCAST 0x08000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define ERXBUF_LONGEVENT 0x10000000
-#define ERXBUF_BADPKT 0x20000000
-#define ERXBUF_GOODPKT 0x40000000
-#define ERXBUF_CARRIER 0x80000000
+#define ERXBUF_LONGEVENT 0x10000000
+#define ERXBUF_BADPKT 0x20000000
+#define ERXBUF_GOODPKT 0x40000000
+#define ERXBUF_CARRIER 0x80000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define ETXD_BYTECNT_MASK 0x000007ff
-#define ETXD_INTWHENDONE 0x00001000
-#define ETXD_D0V 0x00010000
-#define ETXD_B1V 0x00020000
+#define ETXD_BYTECNT_MASK 0x000007ff
+#define ETXD_INTWHENDONE 0x00001000
+#define ETXD_D0V 0x00010000
+#define ETXD_B1V 0x00020000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define ETXD_B2V 0x00040000
-#define ETXD_DOCHECKSUM 0x00080000
-#define ETXD_CHKOFF_MASK 0x07f00000
+#define ETXD_B2V 0x00040000
+#define ETXD_DOCHECKSUM 0x00080000
+#define ETXD_CHKOFF_MASK 0x07f00000
#define ETXD_CHKOFF_SHIFT 20
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ETXD_D0CNT_MASK 0x0000007f