Clean up trailing whitespace in the kernel headers.
And fix the scripts so they stop letting trailing whitespace through.
Change-Id: Ie109fbe1f63321e565ba0fa60fee8e9cf3a61cfc
diff --git a/libc/kernel/arch-mips/asm/pci/bridge.h b/libc/kernel/arch-mips/asm/pci/bridge.h
index cd2fde4..3f421e3 100644
--- a/libc/kernel/arch-mips/asm/pci/bridge.h
+++ b/libc/kernel/arch-mips/asm/pci/bridge.h
@@ -21,24 +21,24 @@
#include <linux/types.h>
#include <linux/pci.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#include <asm/xtalk/xwidget.h>
+#include <asm/xtalk/xwidget.h>
#include <asm/sn/types.h>
-#define IOPFNSHIFT 12
+#define IOPFNSHIFT 12
#define IOPGSIZE (1 << IOPFNSHIFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IOPG(x) ((x) >> IOPFNSHIFT)
#define IOPGOFF(x) ((x) & (IOPGSIZE-1))
-#define BRIDGE_ATE_RAM_SIZE 0x00000400
+#define BRIDGE_ATE_RAM_SIZE 0x00000400
#define BRIDGE_CONFIG_BASE 0x20000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_CONFIG1_BASE 0x28000
#define BRIDGE_CONFIG_END 0x30000
#define BRIDGE_CONFIG_SLOT_SIZE 0x1000
-#define BRIDGE_SSRAM_512K 0x00080000
+#define BRIDGE_SSRAM_512K 0x00080000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define BRIDGE_SSRAM_128K 0x00020000
-#define BRIDGE_SSRAM_64K 0x00010000
-#define BRIDGE_SSRAM_0K 0x00000000
+#define BRIDGE_SSRAM_128K 0x00020000
+#define BRIDGE_SSRAM_64K 0x00010000
+#define BRIDGE_SSRAM_0K 0x00000000
#ifndef __ASSEMBLY__
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
typedef u32 bridgereg_t;
@@ -138,8 +138,8 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
bridgereg_t reg;
} b_rrb_map[2];
-#define b_even_resp b_rrb_map[0].reg
-#define b_odd_resp b_rrb_map[1].reg
+#define b_even_resp b_rrb_map[0].reg
+#define b_odd_resp b_rrb_map[1].reg
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
bridgereg_t _pad_000290;
bridgereg_t b_resp_status;
@@ -256,68 +256,68 @@
#define BRIDGE_WID_LLP WIDGET_LLP_CFG
#define BRIDGE_WID_TFLUSH WIDGET_TFLUSH
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define BRIDGE_WID_AUX_ERR 0x00005C
-#define BRIDGE_WID_RESP_UPPER 0x000064
-#define BRIDGE_WID_RESP_LOWER 0x00006C
-#define BRIDGE_WID_TST_PIN_CTRL 0x000074
+#define BRIDGE_WID_AUX_ERR 0x00005C
+#define BRIDGE_WID_RESP_UPPER 0x000064
+#define BRIDGE_WID_RESP_LOWER 0x00006C
+#define BRIDGE_WID_TST_PIN_CTRL 0x000074
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define BRIDGE_DIR_MAP 0x000084
-#define BRIDGE_RAM_PERR 0x000094
-#define BRIDGE_ARB 0x0000A4
-#define BRIDGE_NIC 0x0000B4
+#define BRIDGE_DIR_MAP 0x000084
+#define BRIDGE_RAM_PERR 0x000094
+#define BRIDGE_ARB 0x0000A4
+#define BRIDGE_NIC 0x0000B4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define BRIDGE_BUS_TIMEOUT 0x0000C4
+#define BRIDGE_BUS_TIMEOUT 0x0000C4
#define BRIDGE_PCI_BUS_TIMEOUT BRIDGE_BUS_TIMEOUT
-#define BRIDGE_PCI_CFG 0x0000CC
-#define BRIDGE_PCI_ERR_UPPER 0x0000D4
+#define BRIDGE_PCI_CFG 0x0000CC
+#define BRIDGE_PCI_ERR_UPPER 0x0000D4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define BRIDGE_PCI_ERR_LOWER 0x0000DC
-#define BRIDGE_INT_STATUS 0x000104
-#define BRIDGE_INT_ENABLE 0x00010C
-#define BRIDGE_INT_RST_STAT 0x000114
+#define BRIDGE_PCI_ERR_LOWER 0x0000DC
+#define BRIDGE_INT_STATUS 0x000104
+#define BRIDGE_INT_ENABLE 0x00010C
+#define BRIDGE_INT_RST_STAT 0x000114
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define BRIDGE_INT_MODE 0x00011C
-#define BRIDGE_INT_DEVICE 0x000124
-#define BRIDGE_INT_HOST_ERR 0x00012C
-#define BRIDGE_INT_ADDR0 0x000134
+#define BRIDGE_INT_MODE 0x00011C
+#define BRIDGE_INT_DEVICE 0x000124
+#define BRIDGE_INT_HOST_ERR 0x00012C
+#define BRIDGE_INT_ADDR0 0x000134
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define BRIDGE_INT_ADDR_OFF 0x000008
+#define BRIDGE_INT_ADDR_OFF 0x000008
#define BRIDGE_INT_ADDR(x) (BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF)
-#define BRIDGE_DEVICE0 0x000204
-#define BRIDGE_DEVICE_OFF 0x000008
+#define BRIDGE_DEVICE0 0x000204
+#define BRIDGE_DEVICE_OFF 0x000008
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_DEVICE(x) (BRIDGE_DEVICE0+(x)*BRIDGE_DEVICE_OFF)
-#define BRIDGE_WR_REQ_BUF0 0x000244
-#define BRIDGE_WR_REQ_BUF_OFF 0x000008
+#define BRIDGE_WR_REQ_BUF0 0x000244
+#define BRIDGE_WR_REQ_BUF_OFF 0x000008
#define BRIDGE_WR_REQ_BUF(x) (BRIDGE_WR_REQ_BUF0+(x)*BRIDGE_WR_REQ_BUF_OFF)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define BRIDGE_EVEN_RESP 0x000284
-#define BRIDGE_ODD_RESP 0x00028C
-#define BRIDGE_RESP_STATUS 0x000294
-#define BRIDGE_RESP_CLEAR 0x00029C
+#define BRIDGE_EVEN_RESP 0x000284
+#define BRIDGE_ODD_RESP 0x00028C
+#define BRIDGE_RESP_STATUS 0x000294
+#define BRIDGE_RESP_CLEAR 0x00029C
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define BRIDGE_ATE_RAM 0x00010000
-#define BRIDGE_TYPE0_CFG_DEV0 0x00020000
-#define BRIDGE_TYPE0_CFG_SLOT_OFF 0x00001000
-#define BRIDGE_TYPE0_CFG_FUNC_OFF 0x00000100
+#define BRIDGE_ATE_RAM 0x00010000
+#define BRIDGE_TYPE0_CFG_DEV0 0x00020000
+#define BRIDGE_TYPE0_CFG_SLOT_OFF 0x00001000
+#define BRIDGE_TYPE0_CFG_FUNC_OFF 0x00000100
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_TYPE0_CFG_DEV(s) (BRIDGE_TYPE0_CFG_DEV0+ (s)*BRIDGE_TYPE0_CFG_SLOT_OFF)
#define BRIDGE_TYPE0_CFG_DEVF(s, f) (BRIDGE_TYPE0_CFG_DEV0+ (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+ (f)*BRIDGE_TYPE0_CFG_FUNC_OFF)
-#define BRIDGE_TYPE1_CFG 0x00028000
-#define BRIDGE_PCI_IACK 0x00030000
+#define BRIDGE_TYPE1_CFG 0x00028000
+#define BRIDGE_PCI_IACK 0x00030000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define BRIDGE_EXT_SSRAM 0x00080000
-#define BRIDGE_DEV_CNT 8
-#define BRIDGE_DEVIO0 0x00200000
-#define BRIDGE_DEVIO1 0x00400000
+#define BRIDGE_EXT_SSRAM 0x00080000
+#define BRIDGE_DEV_CNT 8
+#define BRIDGE_DEVIO0 0x00200000
+#define BRIDGE_DEVIO1 0x00400000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define BRIDGE_DEVIO2 0x00600000
-#define BRIDGE_DEVIO_OFF 0x00100000
-#define BRIDGE_DEVIO_2MB 0x00200000
-#define BRIDGE_DEVIO_1MB 0x00100000
+#define BRIDGE_DEVIO2 0x00600000
+#define BRIDGE_DEVIO_OFF 0x00100000
+#define BRIDGE_DEVIO_2MB 0x00200000
+#define BRIDGE_DEVIO_1MB 0x00100000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_DEVIO(x) ((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB)
-#define BRIDGE_EXTERNAL_FLASH 0x00C00000
+#define BRIDGE_EXTERNAL_FLASH 0x00C00000
#define BRIDGE_WIDGET_PART_NUM 0xc002
#define XBRIDGE_WIDGET_PART_NUM 0xd002
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@@ -384,7 +384,7 @@
#define BRIDGE_DIRMAP_RMF_64 (0x1 << 18)
#define BRIDGE_DIRMAP_ADD512 (0x1 << 17)
#define BRIDGE_DIRMAP_OFF (0x1ffff << 0)
-#define BRIDGE_DIRMAP_OFF_ADDRSHFT (31)
+#define BRIDGE_DIRMAP_OFF_ADDRSHFT (31)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_ARB_REQ_WAIT_TICK(x) ((x) << 16)
#define BRIDGE_ARB_REQ_WAIT_TICK_MASK BRIDGE_ARB_REQ_WAIT_TICK(0x3)
@@ -544,9 +544,9 @@
#define BRIDGE_DEV_PMU_BITS (BRIDGE_DEV_PMU_WRGA_EN | BRIDGE_DEV_SWAP_PMU)
#define BRIDGE_DEV_D32_BITS (BRIDGE_DEV_DIR_WRGA_EN | BRIDGE_DEV_SWAP_DIR | BRIDGE_DEV_PREF | BRIDGE_DEV_PRECISE | BRIDGE_DEV_COH | BRIDGE_DEV_BARRIER)
#define BRIDGE_DEV_D64_BITS (BRIDGE_DEV_DIR_WRGA_EN | BRIDGE_DEV_SWAP_DIR | BRIDGE_DEV_COH | BRIDGE_DEV_BARRIER)
-#define BRIDGE_ERRUPPR_DEVMASTER (0x1 << 20)
+#define BRIDGE_ERRUPPR_DEVMASTER (0x1 << 20)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define BRIDGE_ERRUPPR_PCIVDEV (0x1 << 19)
+#define BRIDGE_ERRUPPR_PCIVDEV (0x1 << 19)
#define BRIDGE_ERRUPPR_DEVNUM_SHFT (16)
#define BRIDGE_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT)
#define BRIDGE_ERRUPPR_DEVICE(err) (((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7)
@@ -554,20 +554,20 @@
#define BRIDGE_ERRUPPR_ADDRMASK (0xFFFF)
#define BRIDGE_INTMODE_CLR_PKT_EN(x) (0x1 << (x))
#define BRIDGE_CREDIT 3
-#define BRIDGE_RRB_EN 0x8
+#define BRIDGE_RRB_EN 0x8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define BRIDGE_RRB_DEV 0x7
-#define BRIDGE_RRB_VDEV 0x4
-#define BRIDGE_RRB_PDEV 0x3
+#define BRIDGE_RRB_DEV 0x7
+#define BRIDGE_RRB_VDEV 0x4
+#define BRIDGE_RRB_PDEV 0x3
#define BRIDGE_RRB_VALID(r) (0x00010000<<(r))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_RRB_INUSE(r) (0x00000001<<(r))
#define BRIDGE_RRB_CLEAR(r) (0x00000001<<(r))
#define XBOX_BRIDGE_WID 8
-#define FLASH_PROM1_BASE 0xE00000
+#define FLASH_PROM1_BASE 0xE00000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define XBOX_RPS_EXISTS 1 << 6
-#define XBOX_RPS_FAIL 1 << 4
+#define XBOX_RPS_EXISTS 1 << 6
+#define XBOX_RPS_FAIL 1 << 4
#define BRIDGE_PIO32_XTALK_ALIAS_BASE 0x000040000000L
#define BRIDGE_PIO32_XTALK_ALIAS_LIMIT 0x00007FFFFFFFL
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@@ -576,9 +576,9 @@
#define BRIDGE_PCIIO_XTALK_ALIAS_BASE 0x000100000000L
#define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT 0x0001FFFFFFFFL
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define BRIDGE_MIN_PIO_ADDR_MEM 0x00000000
+#define BRIDGE_MIN_PIO_ADDR_MEM 0x00000000
#define BRIDGE_MAX_PIO_ADDR_MEM 0x3fffffff
-#define BRIDGE_MIN_PIO_ADDR_IO 0x00000000
+#define BRIDGE_MIN_PIO_ADDR_IO 0x00000000
#define BRIDGE_MAX_PIO_ADDR_IO 0xffffffff
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_PCI_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE
@@ -591,9 +591,9 @@
#define BRIDGE_LOCAL_BASE 0
#define BRIDGE_DMA_MAPPED_BASE 0x40000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define BRIDGE_DMA_MAPPED_SIZE 0x40000000
+#define BRIDGE_DMA_MAPPED_SIZE 0x40000000
#define BRIDGE_DMA_DIRECT_BASE 0x80000000
-#define BRIDGE_DMA_DIRECT_SIZE 0x80000000
+#define BRIDGE_DMA_DIRECT_SIZE 0x80000000
#define PCI32_LOCAL_BASE BRIDGE_LOCAL_BASE
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PCI32_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE