diff --git a/libc/kernel/arch-mips/asm/dma.h b/libc/kernel/arch-mips/asm/dma.h
index aedb5dd..e9ab7b2 100644
--- a/libc/kernel/arch-mips/asm/dma.h
+++ b/libc/kernel/arch-mips/asm/dma.h
@@ -18,8 +18,8 @@
  ****************************************************************************/
 #ifndef _ASM_DMA_H
 #define _ASM_DMA_H
-#include <asm/io.h>  
-#include <linux/spinlock.h>  
+#include <asm/io.h>
+#include <linux/spinlock.h>
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #include <linux/delay.h>
 #include <asm/system.h>
@@ -36,34 +36,34 @@
 #define MAX_DMA_PFN PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS))
 #define MAX_DMA32_PFN (1UL << (32 - PAGE_SHIFT))
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IO_DMA1_BASE 0x00  
-#define IO_DMA2_BASE 0xC0  
-#define DMA1_CMD_REG 0x08  
-#define DMA1_STAT_REG 0x08  
+#define IO_DMA1_BASE 0x00
+#define IO_DMA2_BASE 0xC0
+#define DMA1_CMD_REG 0x08
+#define DMA1_STAT_REG 0x08
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DMA1_REQ_REG 0x09  
-#define DMA1_MASK_REG 0x0A  
-#define DMA1_MODE_REG 0x0B  
-#define DMA1_CLEAR_FF_REG 0x0C  
+#define DMA1_REQ_REG 0x09
+#define DMA1_MASK_REG 0x0A
+#define DMA1_MODE_REG 0x0B
+#define DMA1_CLEAR_FF_REG 0x0C
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DMA1_TEMP_REG 0x0D  
-#define DMA1_RESET_REG 0x0D  
-#define DMA1_CLR_MASK_REG 0x0E  
-#define DMA1_MASK_ALL_REG 0x0F  
+#define DMA1_TEMP_REG 0x0D
+#define DMA1_RESET_REG 0x0D
+#define DMA1_CLR_MASK_REG 0x0E
+#define DMA1_MASK_ALL_REG 0x0F
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DMA2_CMD_REG 0xD0  
-#define DMA2_STAT_REG 0xD0  
-#define DMA2_REQ_REG 0xD2  
-#define DMA2_MASK_REG 0xD4  
+#define DMA2_CMD_REG 0xD0
+#define DMA2_STAT_REG 0xD0
+#define DMA2_REQ_REG 0xD2
+#define DMA2_MASK_REG 0xD4
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DMA2_MODE_REG 0xD6  
-#define DMA2_CLEAR_FF_REG 0xD8  
-#define DMA2_TEMP_REG 0xDA  
-#define DMA2_RESET_REG 0xDA  
+#define DMA2_MODE_REG 0xD6
+#define DMA2_CLEAR_FF_REG 0xD8
+#define DMA2_TEMP_REG 0xDA
+#define DMA2_RESET_REG 0xDA
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DMA2_CLR_MASK_REG 0xDC  
-#define DMA2_MASK_ALL_REG 0xDE  
-#define DMA_ADDR_0 0x00  
+#define DMA2_CLR_MASK_REG 0xDC
+#define DMA2_MASK_ALL_REG 0xDE
+#define DMA_ADDR_0 0x00
 #define DMA_ADDR_1 0x02
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DMA_ADDR_2 0x04
@@ -73,7 +73,7 @@
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DMA_ADDR_6 0xC8
 #define DMA_ADDR_7 0xCC
-#define DMA_CNT_0 0x01  
+#define DMA_CNT_0 0x01
 #define DMA_CNT_1 0x03
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DMA_CNT_2 0x05
@@ -83,7 +83,7 @@
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DMA_CNT_6 0xCA
 #define DMA_CNT_7 0xCE
-#define DMA_PAGE_0 0x87  
+#define DMA_PAGE_0 0x87
 #define DMA_PAGE_1 0x83
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DMA_PAGE_2 0x81
@@ -92,9 +92,9 @@
 #define DMA_PAGE_6 0x89
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DMA_PAGE_7 0x8A
-#define DMA_MODE_READ 0x44  
-#define DMA_MODE_WRITE 0x48  
-#define DMA_MODE_CASCADE 0xC0  
+#define DMA_MODE_READ 0x44
+#define DMA_MODE_WRITE 0x48
+#define DMA_MODE_CASCADE 0xC0
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DMA_AUTOINIT 0x10
 #define isa_dma_bridge_buggy (0)