| commit | c35a0dc08ef0a13a5b4172e981b0b56f527854a1 | [log] [tgz] |
|---|---|---|
| author | Elliott Hughes <enh@google.com> | Tue May 16 16:09:30 2023 -0700 |
| committer | Elliott Hughes <enh@google.com> | Tue May 16 16:09:30 2023 -0700 |
| tree | eb2427f0f2423fa058d55d204e50ec68db50368c | |
| parent | a198c717529cbb4bbc510b1e676eb8ea3e02b4d8 [diff] [blame] |
riscv64: say "x3" rather than "gp" in shadow call stack assembler. Neither is great, but "gp" seems actively misleading (and setjmp.S says x3 every time, so we should be consistent if nothing else). Bug: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/379 Test: treehugger Change-Id: Ibccda74d4794caa770b82e7ba2e31ce7b645b83f
diff --git a/libc/bionic/pthread_create.cpp b/libc/bionic/pthread_create.cpp index 7bf9b40..844f9d8 100644 --- a/libc/bionic/pthread_create.cpp +++ b/libc/bionic/pthread_create.cpp
@@ -140,7 +140,7 @@ #if defined(__aarch64__) __asm__ __volatile__("mov x18, %0" ::"r"(scs)); #elif defined(__riscv) - __asm__ __volatile__("mv gp, %0" ::"r"(scs)); + __asm__ __volatile__("mv x3, %0" ::"r"(scs)); #endif #endif }