Merge "ARM: Change dmb domain for bionic_atomic_barrier()"
diff --git a/libc/private/bionic_atomic_aarch64.h b/libc/private/bionic_atomic_aarch64.h
index c5a9e2e..568382e 100644
--- a/libc/private/bionic_atomic_aarch64.h
+++ b/libc/private/bionic_atomic_aarch64.h
@@ -17,7 +17,7 @@
#define BIONIC_ATOMIC_AARCH64_H
/* For ARMv8, we can use the 'dmb' instruction directly */
-__ATOMIC_INLINE__ void __bionic_memory_barrier(void) {
+__ATOMIC_INLINE__ void __bionic_memory_barrier() {
__asm__ __volatile__ ( "dmb ish" : : : "memory" );
}
diff --git a/libc/private/bionic_atomic_arm.h b/libc/private/bionic_atomic_arm.h
index 023d662..2156e6a 100644
--- a/libc/private/bionic_atomic_arm.h
+++ b/libc/private/bionic_atomic_arm.h
@@ -16,9 +16,9 @@
#ifndef BIONIC_ATOMIC_ARM_H
#define BIONIC_ATOMIC_ARM_H
-__ATOMIC_INLINE__ void __bionic_memory_barrier(void) {
+__ATOMIC_INLINE__ void __bionic_memory_barrier() {
#if defined(ANDROID_SMP) && ANDROID_SMP == 1
- __asm__ __volatile__ ( "dmb" : : : "memory" );
+ __asm__ __volatile__ ( "dmb ish" : : : "memory" );
#else
/* A simple compiler barrier. */
__asm__ __volatile__ ( "" : : : "memory" );
diff --git a/libc/private/bionic_atomic_gcc_builtin.h b/libc/private/bionic_atomic_gcc_builtin.h
index 9e5e5aa..70eb861 100644
--- a/libc/private/bionic_atomic_gcc_builtin.h
+++ b/libc/private/bionic_atomic_gcc_builtin.h
@@ -25,7 +25,7 @@
* the architecture-specific assembler versions.
*/
-__ATOMIC_INLINE__ void __bionic_memory_barrier(void) {
+__ATOMIC_INLINE__ void __bionic_memory_barrier() {
__sync_synchronize();
}
diff --git a/libc/private/bionic_atomic_inline.h b/libc/private/bionic_atomic_inline.h
index 2bb1128..c887e5a 100644
--- a/libc/private/bionic_atomic_inline.h
+++ b/libc/private/bionic_atomic_inline.h
@@ -25,7 +25,7 @@
*
* Macros defined in this header:
*
- * void ANDROID_MEMBAR_FULL(void)
+ * void ANDROID_MEMBAR_FULL()
* Full memory barrier. Provides a compiler reordering barrier, and
* on SMP systems emits an appropriate instruction.
*/