diff --git a/libc/kernel/uapi/drm/amdgpu_drm.h b/libc/kernel/uapi/drm/amdgpu_drm.h
index fcd5ab8..8d0d0b0 100644
--- a/libc/kernel/uapi/drm/amdgpu_drm.h
+++ b/libc/kernel/uapi/drm/amdgpu_drm.h
@@ -428,6 +428,7 @@
 #define AMDGPU_IDS_FLAGS_FUSION 0x1
 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2
 #define AMDGPU_IDS_FLAGS_TMZ 0x4
+#define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8
 #define AMDGPU_INFO_ACCEL_WORKING 0x00
 #define AMDGPU_INFO_CRTC_FROM_ID 0x01
 #define AMDGPU_INFO_HW_IP_INFO 0x02
@@ -486,6 +487,8 @@
 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7
 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8
 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9
+#define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa
+#define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb
 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20
@@ -616,7 +619,7 @@
   __u32 enabled_rb_pipes_mask;
   __u32 num_rb_pipes;
   __u32 num_hw_gfx_contexts;
-  __u32 _pad;
+  __u32 pcie_gen;
   __u64 ids_flags;
   __u64 virtual_address_offset;
   __u64 virtual_address_max;
@@ -643,12 +646,22 @@
   __u32 gs_vgt_table_depth;
   __u32 gs_prim_buffer_depth;
   __u32 max_gs_waves_per_vgt;
-  __u32 _pad1;
+  __u32 pcie_num_lanes;
   __u32 cu_ao_bitmap[4][4];
   __u64 high_va_offset;
   __u64 high_va_max;
   __u32 pa_sc_tile_steering_override;
   __u64 tcc_disabled_mask;
+  __u64 min_engine_clock;
+  __u64 min_memory_clock;
+  __u32 tcp_cache_size;
+  __u32 num_sqc_per_wgp;
+  __u32 sqc_data_cache_size;
+  __u32 sqc_inst_cache_size;
+  __u32 gl1c_cache_size;
+  __u32 gl2c_cache_size;
+  __u64 mall_size;
+  __u32 enabled_rb_pipes_mask_hi;
 };
 struct drm_amdgpu_info_hw_ip {
   __u32 hw_ip_version_major;
diff --git a/libc/kernel/uapi/drm/habanalabs_accel.h b/libc/kernel/uapi/drm/habanalabs_accel.h
new file mode 100644
index 0000000..d7dccef
--- /dev/null
+++ b/libc/kernel/uapi/drm/habanalabs_accel.h
@@ -0,0 +1,1170 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ***   To edit the content of this header, modify the corresponding
+ ***   source file (e.g. under external/kernel-headers/original/) then
+ ***   run bionic/libc/kernel/tools/update_all.py
+ ***
+ ***   Any manual change here will be lost the next time this script will
+ ***   be run. You've been warned!
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef HABANALABS_H_
+#define HABANALABS_H_
+#include <linux/types.h>
+#include <linux/ioctl.h>
+#define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000
+#define GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START 0x80
+#define GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT 144
+#define GAUDI_FIRST_AVAILABLE_W_S_MONITOR 72
+#define TS_MAX_ELEMENTS_NUM (1 << 20)
+enum goya_queue_id {
+  GOYA_QUEUE_ID_DMA_0 = 0,
+  GOYA_QUEUE_ID_DMA_1 = 1,
+  GOYA_QUEUE_ID_DMA_2 = 2,
+  GOYA_QUEUE_ID_DMA_3 = 3,
+  GOYA_QUEUE_ID_DMA_4 = 4,
+  GOYA_QUEUE_ID_CPU_PQ = 5,
+  GOYA_QUEUE_ID_MME = 6,
+  GOYA_QUEUE_ID_TPC0 = 7,
+  GOYA_QUEUE_ID_TPC1 = 8,
+  GOYA_QUEUE_ID_TPC2 = 9,
+  GOYA_QUEUE_ID_TPC3 = 10,
+  GOYA_QUEUE_ID_TPC4 = 11,
+  GOYA_QUEUE_ID_TPC5 = 12,
+  GOYA_QUEUE_ID_TPC6 = 13,
+  GOYA_QUEUE_ID_TPC7 = 14,
+  GOYA_QUEUE_ID_SIZE
+};
+enum gaudi_queue_id {
+  GAUDI_QUEUE_ID_DMA_0_0 = 0,
+  GAUDI_QUEUE_ID_DMA_0_1 = 1,
+  GAUDI_QUEUE_ID_DMA_0_2 = 2,
+  GAUDI_QUEUE_ID_DMA_0_3 = 3,
+  GAUDI_QUEUE_ID_DMA_1_0 = 4,
+  GAUDI_QUEUE_ID_DMA_1_1 = 5,
+  GAUDI_QUEUE_ID_DMA_1_2 = 6,
+  GAUDI_QUEUE_ID_DMA_1_3 = 7,
+  GAUDI_QUEUE_ID_CPU_PQ = 8,
+  GAUDI_QUEUE_ID_DMA_2_0 = 9,
+  GAUDI_QUEUE_ID_DMA_2_1 = 10,
+  GAUDI_QUEUE_ID_DMA_2_2 = 11,
+  GAUDI_QUEUE_ID_DMA_2_3 = 12,
+  GAUDI_QUEUE_ID_DMA_3_0 = 13,
+  GAUDI_QUEUE_ID_DMA_3_1 = 14,
+  GAUDI_QUEUE_ID_DMA_3_2 = 15,
+  GAUDI_QUEUE_ID_DMA_3_3 = 16,
+  GAUDI_QUEUE_ID_DMA_4_0 = 17,
+  GAUDI_QUEUE_ID_DMA_4_1 = 18,
+  GAUDI_QUEUE_ID_DMA_4_2 = 19,
+  GAUDI_QUEUE_ID_DMA_4_3 = 20,
+  GAUDI_QUEUE_ID_DMA_5_0 = 21,
+  GAUDI_QUEUE_ID_DMA_5_1 = 22,
+  GAUDI_QUEUE_ID_DMA_5_2 = 23,
+  GAUDI_QUEUE_ID_DMA_5_3 = 24,
+  GAUDI_QUEUE_ID_DMA_6_0 = 25,
+  GAUDI_QUEUE_ID_DMA_6_1 = 26,
+  GAUDI_QUEUE_ID_DMA_6_2 = 27,
+  GAUDI_QUEUE_ID_DMA_6_3 = 28,
+  GAUDI_QUEUE_ID_DMA_7_0 = 29,
+  GAUDI_QUEUE_ID_DMA_7_1 = 30,
+  GAUDI_QUEUE_ID_DMA_7_2 = 31,
+  GAUDI_QUEUE_ID_DMA_7_3 = 32,
+  GAUDI_QUEUE_ID_MME_0_0 = 33,
+  GAUDI_QUEUE_ID_MME_0_1 = 34,
+  GAUDI_QUEUE_ID_MME_0_2 = 35,
+  GAUDI_QUEUE_ID_MME_0_3 = 36,
+  GAUDI_QUEUE_ID_MME_1_0 = 37,
+  GAUDI_QUEUE_ID_MME_1_1 = 38,
+  GAUDI_QUEUE_ID_MME_1_2 = 39,
+  GAUDI_QUEUE_ID_MME_1_3 = 40,
+  GAUDI_QUEUE_ID_TPC_0_0 = 41,
+  GAUDI_QUEUE_ID_TPC_0_1 = 42,
+  GAUDI_QUEUE_ID_TPC_0_2 = 43,
+  GAUDI_QUEUE_ID_TPC_0_3 = 44,
+  GAUDI_QUEUE_ID_TPC_1_0 = 45,
+  GAUDI_QUEUE_ID_TPC_1_1 = 46,
+  GAUDI_QUEUE_ID_TPC_1_2 = 47,
+  GAUDI_QUEUE_ID_TPC_1_3 = 48,
+  GAUDI_QUEUE_ID_TPC_2_0 = 49,
+  GAUDI_QUEUE_ID_TPC_2_1 = 50,
+  GAUDI_QUEUE_ID_TPC_2_2 = 51,
+  GAUDI_QUEUE_ID_TPC_2_3 = 52,
+  GAUDI_QUEUE_ID_TPC_3_0 = 53,
+  GAUDI_QUEUE_ID_TPC_3_1 = 54,
+  GAUDI_QUEUE_ID_TPC_3_2 = 55,
+  GAUDI_QUEUE_ID_TPC_3_3 = 56,
+  GAUDI_QUEUE_ID_TPC_4_0 = 57,
+  GAUDI_QUEUE_ID_TPC_4_1 = 58,
+  GAUDI_QUEUE_ID_TPC_4_2 = 59,
+  GAUDI_QUEUE_ID_TPC_4_3 = 60,
+  GAUDI_QUEUE_ID_TPC_5_0 = 61,
+  GAUDI_QUEUE_ID_TPC_5_1 = 62,
+  GAUDI_QUEUE_ID_TPC_5_2 = 63,
+  GAUDI_QUEUE_ID_TPC_5_3 = 64,
+  GAUDI_QUEUE_ID_TPC_6_0 = 65,
+  GAUDI_QUEUE_ID_TPC_6_1 = 66,
+  GAUDI_QUEUE_ID_TPC_6_2 = 67,
+  GAUDI_QUEUE_ID_TPC_6_3 = 68,
+  GAUDI_QUEUE_ID_TPC_7_0 = 69,
+  GAUDI_QUEUE_ID_TPC_7_1 = 70,
+  GAUDI_QUEUE_ID_TPC_7_2 = 71,
+  GAUDI_QUEUE_ID_TPC_7_3 = 72,
+  GAUDI_QUEUE_ID_NIC_0_0 = 73,
+  GAUDI_QUEUE_ID_NIC_0_1 = 74,
+  GAUDI_QUEUE_ID_NIC_0_2 = 75,
+  GAUDI_QUEUE_ID_NIC_0_3 = 76,
+  GAUDI_QUEUE_ID_NIC_1_0 = 77,
+  GAUDI_QUEUE_ID_NIC_1_1 = 78,
+  GAUDI_QUEUE_ID_NIC_1_2 = 79,
+  GAUDI_QUEUE_ID_NIC_1_3 = 80,
+  GAUDI_QUEUE_ID_NIC_2_0 = 81,
+  GAUDI_QUEUE_ID_NIC_2_1 = 82,
+  GAUDI_QUEUE_ID_NIC_2_2 = 83,
+  GAUDI_QUEUE_ID_NIC_2_3 = 84,
+  GAUDI_QUEUE_ID_NIC_3_0 = 85,
+  GAUDI_QUEUE_ID_NIC_3_1 = 86,
+  GAUDI_QUEUE_ID_NIC_3_2 = 87,
+  GAUDI_QUEUE_ID_NIC_3_3 = 88,
+  GAUDI_QUEUE_ID_NIC_4_0 = 89,
+  GAUDI_QUEUE_ID_NIC_4_1 = 90,
+  GAUDI_QUEUE_ID_NIC_4_2 = 91,
+  GAUDI_QUEUE_ID_NIC_4_3 = 92,
+  GAUDI_QUEUE_ID_NIC_5_0 = 93,
+  GAUDI_QUEUE_ID_NIC_5_1 = 94,
+  GAUDI_QUEUE_ID_NIC_5_2 = 95,
+  GAUDI_QUEUE_ID_NIC_5_3 = 96,
+  GAUDI_QUEUE_ID_NIC_6_0 = 97,
+  GAUDI_QUEUE_ID_NIC_6_1 = 98,
+  GAUDI_QUEUE_ID_NIC_6_2 = 99,
+  GAUDI_QUEUE_ID_NIC_6_3 = 100,
+  GAUDI_QUEUE_ID_NIC_7_0 = 101,
+  GAUDI_QUEUE_ID_NIC_7_1 = 102,
+  GAUDI_QUEUE_ID_NIC_7_2 = 103,
+  GAUDI_QUEUE_ID_NIC_7_3 = 104,
+  GAUDI_QUEUE_ID_NIC_8_0 = 105,
+  GAUDI_QUEUE_ID_NIC_8_1 = 106,
+  GAUDI_QUEUE_ID_NIC_8_2 = 107,
+  GAUDI_QUEUE_ID_NIC_8_3 = 108,
+  GAUDI_QUEUE_ID_NIC_9_0 = 109,
+  GAUDI_QUEUE_ID_NIC_9_1 = 110,
+  GAUDI_QUEUE_ID_NIC_9_2 = 111,
+  GAUDI_QUEUE_ID_NIC_9_3 = 112,
+  GAUDI_QUEUE_ID_SIZE
+};
+enum gaudi2_queue_id {
+  GAUDI2_QUEUE_ID_PDMA_0_0 = 0,
+  GAUDI2_QUEUE_ID_PDMA_0_1 = 1,
+  GAUDI2_QUEUE_ID_PDMA_0_2 = 2,
+  GAUDI2_QUEUE_ID_PDMA_0_3 = 3,
+  GAUDI2_QUEUE_ID_PDMA_1_0 = 4,
+  GAUDI2_QUEUE_ID_PDMA_1_1 = 5,
+  GAUDI2_QUEUE_ID_PDMA_1_2 = 6,
+  GAUDI2_QUEUE_ID_PDMA_1_3 = 7,
+  GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0 = 8,
+  GAUDI2_QUEUE_ID_DCORE0_EDMA_0_1 = 9,
+  GAUDI2_QUEUE_ID_DCORE0_EDMA_0_2 = 10,
+  GAUDI2_QUEUE_ID_DCORE0_EDMA_0_3 = 11,
+  GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0 = 12,
+  GAUDI2_QUEUE_ID_DCORE0_EDMA_1_1 = 13,
+  GAUDI2_QUEUE_ID_DCORE0_EDMA_1_2 = 14,
+  GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3 = 15,
+  GAUDI2_QUEUE_ID_DCORE0_MME_0_0 = 16,
+  GAUDI2_QUEUE_ID_DCORE0_MME_0_1 = 17,
+  GAUDI2_QUEUE_ID_DCORE0_MME_0_2 = 18,
+  GAUDI2_QUEUE_ID_DCORE0_MME_0_3 = 19,
+  GAUDI2_QUEUE_ID_DCORE0_TPC_0_0 = 20,
+  GAUDI2_QUEUE_ID_DCORE0_TPC_0_1 = 21,
+  GAUDI2_QUEUE_ID_DCORE0_TPC_0_2 = 22,
+  GAUDI2_QUEUE_ID_DCORE0_TPC_0_3 = 23,
+  GAUDI2_QUEUE_ID_DCORE0_TPC_1_0 = 24,
+  GAUDI2_QUEUE_ID_DCORE0_TPC_1_1 = 25,
+  GAUDI2_QUEUE_ID_DCORE0_TPC_1_2 = 26,
+  GAUDI2_QUEUE_ID_DCORE0_TPC_1_3 = 27,
+  GAUDI2_QUEUE_ID_DCORE0_TPC_2_0 = 28,
+  GAUDI2_QUEUE_ID_DCORE0_TPC_2_1 = 29,
+  GAUDI2_QUEUE_ID_DCORE0_TPC_2_2 = 30,
+  GAUDI2_QUEUE_ID_DCORE0_TPC_2_3 = 31,
+  GAUDI2_QUEUE_ID_DCORE0_TPC_3_0 = 32,
+  GAUDI2_QUEUE_ID_DCORE0_TPC_3_1 = 33,
+  GAUDI2_QUEUE_ID_DCORE0_TPC_3_2 = 34,
+  GAUDI2_QUEUE_ID_DCORE0_TPC_3_3 = 35,
+  GAUDI2_QUEUE_ID_DCORE0_TPC_4_0 = 36,
+  GAUDI2_QUEUE_ID_DCORE0_TPC_4_1 = 37,
+  GAUDI2_QUEUE_ID_DCORE0_TPC_4_2 = 38,
+  GAUDI2_QUEUE_ID_DCORE0_TPC_4_3 = 39,
+  GAUDI2_QUEUE_ID_DCORE0_TPC_5_0 = 40,
+  GAUDI2_QUEUE_ID_DCORE0_TPC_5_1 = 41,
+  GAUDI2_QUEUE_ID_DCORE0_TPC_5_2 = 42,
+  GAUDI2_QUEUE_ID_DCORE0_TPC_5_3 = 43,
+  GAUDI2_QUEUE_ID_DCORE0_TPC_6_0 = 44,
+  GAUDI2_QUEUE_ID_DCORE0_TPC_6_1 = 45,
+  GAUDI2_QUEUE_ID_DCORE0_TPC_6_2 = 46,
+  GAUDI2_QUEUE_ID_DCORE0_TPC_6_3 = 47,
+  GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0 = 48,
+  GAUDI2_QUEUE_ID_DCORE1_EDMA_0_1 = 49,
+  GAUDI2_QUEUE_ID_DCORE1_EDMA_0_2 = 50,
+  GAUDI2_QUEUE_ID_DCORE1_EDMA_0_3 = 51,
+  GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0 = 52,
+  GAUDI2_QUEUE_ID_DCORE1_EDMA_1_1 = 53,
+  GAUDI2_QUEUE_ID_DCORE1_EDMA_1_2 = 54,
+  GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3 = 55,
+  GAUDI2_QUEUE_ID_DCORE1_MME_0_0 = 56,
+  GAUDI2_QUEUE_ID_DCORE1_MME_0_1 = 57,
+  GAUDI2_QUEUE_ID_DCORE1_MME_0_2 = 58,
+  GAUDI2_QUEUE_ID_DCORE1_MME_0_3 = 59,
+  GAUDI2_QUEUE_ID_DCORE1_TPC_0_0 = 60,
+  GAUDI2_QUEUE_ID_DCORE1_TPC_0_1 = 61,
+  GAUDI2_QUEUE_ID_DCORE1_TPC_0_2 = 62,
+  GAUDI2_QUEUE_ID_DCORE1_TPC_0_3 = 63,
+  GAUDI2_QUEUE_ID_DCORE1_TPC_1_0 = 64,
+  GAUDI2_QUEUE_ID_DCORE1_TPC_1_1 = 65,
+  GAUDI2_QUEUE_ID_DCORE1_TPC_1_2 = 66,
+  GAUDI2_QUEUE_ID_DCORE1_TPC_1_3 = 67,
+  GAUDI2_QUEUE_ID_DCORE1_TPC_2_0 = 68,
+  GAUDI2_QUEUE_ID_DCORE1_TPC_2_1 = 69,
+  GAUDI2_QUEUE_ID_DCORE1_TPC_2_2 = 70,
+  GAUDI2_QUEUE_ID_DCORE1_TPC_2_3 = 71,
+  GAUDI2_QUEUE_ID_DCORE1_TPC_3_0 = 72,
+  GAUDI2_QUEUE_ID_DCORE1_TPC_3_1 = 73,
+  GAUDI2_QUEUE_ID_DCORE1_TPC_3_2 = 74,
+  GAUDI2_QUEUE_ID_DCORE1_TPC_3_3 = 75,
+  GAUDI2_QUEUE_ID_DCORE1_TPC_4_0 = 76,
+  GAUDI2_QUEUE_ID_DCORE1_TPC_4_1 = 77,
+  GAUDI2_QUEUE_ID_DCORE1_TPC_4_2 = 78,
+  GAUDI2_QUEUE_ID_DCORE1_TPC_4_3 = 79,
+  GAUDI2_QUEUE_ID_DCORE1_TPC_5_0 = 80,
+  GAUDI2_QUEUE_ID_DCORE1_TPC_5_1 = 81,
+  GAUDI2_QUEUE_ID_DCORE1_TPC_5_2 = 82,
+  GAUDI2_QUEUE_ID_DCORE1_TPC_5_3 = 83,
+  GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0 = 84,
+  GAUDI2_QUEUE_ID_DCORE2_EDMA_0_1 = 85,
+  GAUDI2_QUEUE_ID_DCORE2_EDMA_0_2 = 86,
+  GAUDI2_QUEUE_ID_DCORE2_EDMA_0_3 = 87,
+  GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0 = 88,
+  GAUDI2_QUEUE_ID_DCORE2_EDMA_1_1 = 89,
+  GAUDI2_QUEUE_ID_DCORE2_EDMA_1_2 = 90,
+  GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3 = 91,
+  GAUDI2_QUEUE_ID_DCORE2_MME_0_0 = 92,
+  GAUDI2_QUEUE_ID_DCORE2_MME_0_1 = 93,
+  GAUDI2_QUEUE_ID_DCORE2_MME_0_2 = 94,
+  GAUDI2_QUEUE_ID_DCORE2_MME_0_3 = 95,
+  GAUDI2_QUEUE_ID_DCORE2_TPC_0_0 = 96,
+  GAUDI2_QUEUE_ID_DCORE2_TPC_0_1 = 97,
+  GAUDI2_QUEUE_ID_DCORE2_TPC_0_2 = 98,
+  GAUDI2_QUEUE_ID_DCORE2_TPC_0_3 = 99,
+  GAUDI2_QUEUE_ID_DCORE2_TPC_1_0 = 100,
+  GAUDI2_QUEUE_ID_DCORE2_TPC_1_1 = 101,
+  GAUDI2_QUEUE_ID_DCORE2_TPC_1_2 = 102,
+  GAUDI2_QUEUE_ID_DCORE2_TPC_1_3 = 103,
+  GAUDI2_QUEUE_ID_DCORE2_TPC_2_0 = 104,
+  GAUDI2_QUEUE_ID_DCORE2_TPC_2_1 = 105,
+  GAUDI2_QUEUE_ID_DCORE2_TPC_2_2 = 106,
+  GAUDI2_QUEUE_ID_DCORE2_TPC_2_3 = 107,
+  GAUDI2_QUEUE_ID_DCORE2_TPC_3_0 = 108,
+  GAUDI2_QUEUE_ID_DCORE2_TPC_3_1 = 109,
+  GAUDI2_QUEUE_ID_DCORE2_TPC_3_2 = 110,
+  GAUDI2_QUEUE_ID_DCORE2_TPC_3_3 = 111,
+  GAUDI2_QUEUE_ID_DCORE2_TPC_4_0 = 112,
+  GAUDI2_QUEUE_ID_DCORE2_TPC_4_1 = 113,
+  GAUDI2_QUEUE_ID_DCORE2_TPC_4_2 = 114,
+  GAUDI2_QUEUE_ID_DCORE2_TPC_4_3 = 115,
+  GAUDI2_QUEUE_ID_DCORE2_TPC_5_0 = 116,
+  GAUDI2_QUEUE_ID_DCORE2_TPC_5_1 = 117,
+  GAUDI2_QUEUE_ID_DCORE2_TPC_5_2 = 118,
+  GAUDI2_QUEUE_ID_DCORE2_TPC_5_3 = 119,
+  GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0 = 120,
+  GAUDI2_QUEUE_ID_DCORE3_EDMA_0_1 = 121,
+  GAUDI2_QUEUE_ID_DCORE3_EDMA_0_2 = 122,
+  GAUDI2_QUEUE_ID_DCORE3_EDMA_0_3 = 123,
+  GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0 = 124,
+  GAUDI2_QUEUE_ID_DCORE3_EDMA_1_1 = 125,
+  GAUDI2_QUEUE_ID_DCORE3_EDMA_1_2 = 126,
+  GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3 = 127,
+  GAUDI2_QUEUE_ID_DCORE3_MME_0_0 = 128,
+  GAUDI2_QUEUE_ID_DCORE3_MME_0_1 = 129,
+  GAUDI2_QUEUE_ID_DCORE3_MME_0_2 = 130,
+  GAUDI2_QUEUE_ID_DCORE3_MME_0_3 = 131,
+  GAUDI2_QUEUE_ID_DCORE3_TPC_0_0 = 132,
+  GAUDI2_QUEUE_ID_DCORE3_TPC_0_1 = 133,
+  GAUDI2_QUEUE_ID_DCORE3_TPC_0_2 = 134,
+  GAUDI2_QUEUE_ID_DCORE3_TPC_0_3 = 135,
+  GAUDI2_QUEUE_ID_DCORE3_TPC_1_0 = 136,
+  GAUDI2_QUEUE_ID_DCORE3_TPC_1_1 = 137,
+  GAUDI2_QUEUE_ID_DCORE3_TPC_1_2 = 138,
+  GAUDI2_QUEUE_ID_DCORE3_TPC_1_3 = 139,
+  GAUDI2_QUEUE_ID_DCORE3_TPC_2_0 = 140,
+  GAUDI2_QUEUE_ID_DCORE3_TPC_2_1 = 141,
+  GAUDI2_QUEUE_ID_DCORE3_TPC_2_2 = 142,
+  GAUDI2_QUEUE_ID_DCORE3_TPC_2_3 = 143,
+  GAUDI2_QUEUE_ID_DCORE3_TPC_3_0 = 144,
+  GAUDI2_QUEUE_ID_DCORE3_TPC_3_1 = 145,
+  GAUDI2_QUEUE_ID_DCORE3_TPC_3_2 = 146,
+  GAUDI2_QUEUE_ID_DCORE3_TPC_3_3 = 147,
+  GAUDI2_QUEUE_ID_DCORE3_TPC_4_0 = 148,
+  GAUDI2_QUEUE_ID_DCORE3_TPC_4_1 = 149,
+  GAUDI2_QUEUE_ID_DCORE3_TPC_4_2 = 150,
+  GAUDI2_QUEUE_ID_DCORE3_TPC_4_3 = 151,
+  GAUDI2_QUEUE_ID_DCORE3_TPC_5_0 = 152,
+  GAUDI2_QUEUE_ID_DCORE3_TPC_5_1 = 153,
+  GAUDI2_QUEUE_ID_DCORE3_TPC_5_2 = 154,
+  GAUDI2_QUEUE_ID_DCORE3_TPC_5_3 = 155,
+  GAUDI2_QUEUE_ID_NIC_0_0 = 156,
+  GAUDI2_QUEUE_ID_NIC_0_1 = 157,
+  GAUDI2_QUEUE_ID_NIC_0_2 = 158,
+  GAUDI2_QUEUE_ID_NIC_0_3 = 159,
+  GAUDI2_QUEUE_ID_NIC_1_0 = 160,
+  GAUDI2_QUEUE_ID_NIC_1_1 = 161,
+  GAUDI2_QUEUE_ID_NIC_1_2 = 162,
+  GAUDI2_QUEUE_ID_NIC_1_3 = 163,
+  GAUDI2_QUEUE_ID_NIC_2_0 = 164,
+  GAUDI2_QUEUE_ID_NIC_2_1 = 165,
+  GAUDI2_QUEUE_ID_NIC_2_2 = 166,
+  GAUDI2_QUEUE_ID_NIC_2_3 = 167,
+  GAUDI2_QUEUE_ID_NIC_3_0 = 168,
+  GAUDI2_QUEUE_ID_NIC_3_1 = 169,
+  GAUDI2_QUEUE_ID_NIC_3_2 = 170,
+  GAUDI2_QUEUE_ID_NIC_3_3 = 171,
+  GAUDI2_QUEUE_ID_NIC_4_0 = 172,
+  GAUDI2_QUEUE_ID_NIC_4_1 = 173,
+  GAUDI2_QUEUE_ID_NIC_4_2 = 174,
+  GAUDI2_QUEUE_ID_NIC_4_3 = 175,
+  GAUDI2_QUEUE_ID_NIC_5_0 = 176,
+  GAUDI2_QUEUE_ID_NIC_5_1 = 177,
+  GAUDI2_QUEUE_ID_NIC_5_2 = 178,
+  GAUDI2_QUEUE_ID_NIC_5_3 = 179,
+  GAUDI2_QUEUE_ID_NIC_6_0 = 180,
+  GAUDI2_QUEUE_ID_NIC_6_1 = 181,
+  GAUDI2_QUEUE_ID_NIC_6_2 = 182,
+  GAUDI2_QUEUE_ID_NIC_6_3 = 183,
+  GAUDI2_QUEUE_ID_NIC_7_0 = 184,
+  GAUDI2_QUEUE_ID_NIC_7_1 = 185,
+  GAUDI2_QUEUE_ID_NIC_7_2 = 186,
+  GAUDI2_QUEUE_ID_NIC_7_3 = 187,
+  GAUDI2_QUEUE_ID_NIC_8_0 = 188,
+  GAUDI2_QUEUE_ID_NIC_8_1 = 189,
+  GAUDI2_QUEUE_ID_NIC_8_2 = 190,
+  GAUDI2_QUEUE_ID_NIC_8_3 = 191,
+  GAUDI2_QUEUE_ID_NIC_9_0 = 192,
+  GAUDI2_QUEUE_ID_NIC_9_1 = 193,
+  GAUDI2_QUEUE_ID_NIC_9_2 = 194,
+  GAUDI2_QUEUE_ID_NIC_9_3 = 195,
+  GAUDI2_QUEUE_ID_NIC_10_0 = 196,
+  GAUDI2_QUEUE_ID_NIC_10_1 = 197,
+  GAUDI2_QUEUE_ID_NIC_10_2 = 198,
+  GAUDI2_QUEUE_ID_NIC_10_3 = 199,
+  GAUDI2_QUEUE_ID_NIC_11_0 = 200,
+  GAUDI2_QUEUE_ID_NIC_11_1 = 201,
+  GAUDI2_QUEUE_ID_NIC_11_2 = 202,
+  GAUDI2_QUEUE_ID_NIC_11_3 = 203,
+  GAUDI2_QUEUE_ID_NIC_12_0 = 204,
+  GAUDI2_QUEUE_ID_NIC_12_1 = 205,
+  GAUDI2_QUEUE_ID_NIC_12_2 = 206,
+  GAUDI2_QUEUE_ID_NIC_12_3 = 207,
+  GAUDI2_QUEUE_ID_NIC_13_0 = 208,
+  GAUDI2_QUEUE_ID_NIC_13_1 = 209,
+  GAUDI2_QUEUE_ID_NIC_13_2 = 210,
+  GAUDI2_QUEUE_ID_NIC_13_3 = 211,
+  GAUDI2_QUEUE_ID_NIC_14_0 = 212,
+  GAUDI2_QUEUE_ID_NIC_14_1 = 213,
+  GAUDI2_QUEUE_ID_NIC_14_2 = 214,
+  GAUDI2_QUEUE_ID_NIC_14_3 = 215,
+  GAUDI2_QUEUE_ID_NIC_15_0 = 216,
+  GAUDI2_QUEUE_ID_NIC_15_1 = 217,
+  GAUDI2_QUEUE_ID_NIC_15_2 = 218,
+  GAUDI2_QUEUE_ID_NIC_15_3 = 219,
+  GAUDI2_QUEUE_ID_NIC_16_0 = 220,
+  GAUDI2_QUEUE_ID_NIC_16_1 = 221,
+  GAUDI2_QUEUE_ID_NIC_16_2 = 222,
+  GAUDI2_QUEUE_ID_NIC_16_3 = 223,
+  GAUDI2_QUEUE_ID_NIC_17_0 = 224,
+  GAUDI2_QUEUE_ID_NIC_17_1 = 225,
+  GAUDI2_QUEUE_ID_NIC_17_2 = 226,
+  GAUDI2_QUEUE_ID_NIC_17_3 = 227,
+  GAUDI2_QUEUE_ID_NIC_18_0 = 228,
+  GAUDI2_QUEUE_ID_NIC_18_1 = 229,
+  GAUDI2_QUEUE_ID_NIC_18_2 = 230,
+  GAUDI2_QUEUE_ID_NIC_18_3 = 231,
+  GAUDI2_QUEUE_ID_NIC_19_0 = 232,
+  GAUDI2_QUEUE_ID_NIC_19_1 = 233,
+  GAUDI2_QUEUE_ID_NIC_19_2 = 234,
+  GAUDI2_QUEUE_ID_NIC_19_3 = 235,
+  GAUDI2_QUEUE_ID_NIC_20_0 = 236,
+  GAUDI2_QUEUE_ID_NIC_20_1 = 237,
+  GAUDI2_QUEUE_ID_NIC_20_2 = 238,
+  GAUDI2_QUEUE_ID_NIC_20_3 = 239,
+  GAUDI2_QUEUE_ID_NIC_21_0 = 240,
+  GAUDI2_QUEUE_ID_NIC_21_1 = 241,
+  GAUDI2_QUEUE_ID_NIC_21_2 = 242,
+  GAUDI2_QUEUE_ID_NIC_21_3 = 243,
+  GAUDI2_QUEUE_ID_NIC_22_0 = 244,
+  GAUDI2_QUEUE_ID_NIC_22_1 = 245,
+  GAUDI2_QUEUE_ID_NIC_22_2 = 246,
+  GAUDI2_QUEUE_ID_NIC_22_3 = 247,
+  GAUDI2_QUEUE_ID_NIC_23_0 = 248,
+  GAUDI2_QUEUE_ID_NIC_23_1 = 249,
+  GAUDI2_QUEUE_ID_NIC_23_2 = 250,
+  GAUDI2_QUEUE_ID_NIC_23_3 = 251,
+  GAUDI2_QUEUE_ID_ROT_0_0 = 252,
+  GAUDI2_QUEUE_ID_ROT_0_1 = 253,
+  GAUDI2_QUEUE_ID_ROT_0_2 = 254,
+  GAUDI2_QUEUE_ID_ROT_0_3 = 255,
+  GAUDI2_QUEUE_ID_ROT_1_0 = 256,
+  GAUDI2_QUEUE_ID_ROT_1_1 = 257,
+  GAUDI2_QUEUE_ID_ROT_1_2 = 258,
+  GAUDI2_QUEUE_ID_ROT_1_3 = 259,
+  GAUDI2_QUEUE_ID_CPU_PQ = 260,
+  GAUDI2_QUEUE_ID_SIZE
+};
+enum goya_engine_id {
+  GOYA_ENGINE_ID_DMA_0 = 0,
+  GOYA_ENGINE_ID_DMA_1,
+  GOYA_ENGINE_ID_DMA_2,
+  GOYA_ENGINE_ID_DMA_3,
+  GOYA_ENGINE_ID_DMA_4,
+  GOYA_ENGINE_ID_MME_0,
+  GOYA_ENGINE_ID_TPC_0,
+  GOYA_ENGINE_ID_TPC_1,
+  GOYA_ENGINE_ID_TPC_2,
+  GOYA_ENGINE_ID_TPC_3,
+  GOYA_ENGINE_ID_TPC_4,
+  GOYA_ENGINE_ID_TPC_5,
+  GOYA_ENGINE_ID_TPC_6,
+  GOYA_ENGINE_ID_TPC_7,
+  GOYA_ENGINE_ID_SIZE
+};
+enum gaudi_engine_id {
+  GAUDI_ENGINE_ID_DMA_0 = 0,
+  GAUDI_ENGINE_ID_DMA_1,
+  GAUDI_ENGINE_ID_DMA_2,
+  GAUDI_ENGINE_ID_DMA_3,
+  GAUDI_ENGINE_ID_DMA_4,
+  GAUDI_ENGINE_ID_DMA_5,
+  GAUDI_ENGINE_ID_DMA_6,
+  GAUDI_ENGINE_ID_DMA_7,
+  GAUDI_ENGINE_ID_MME_0,
+  GAUDI_ENGINE_ID_MME_1,
+  GAUDI_ENGINE_ID_MME_2,
+  GAUDI_ENGINE_ID_MME_3,
+  GAUDI_ENGINE_ID_TPC_0,
+  GAUDI_ENGINE_ID_TPC_1,
+  GAUDI_ENGINE_ID_TPC_2,
+  GAUDI_ENGINE_ID_TPC_3,
+  GAUDI_ENGINE_ID_TPC_4,
+  GAUDI_ENGINE_ID_TPC_5,
+  GAUDI_ENGINE_ID_TPC_6,
+  GAUDI_ENGINE_ID_TPC_7,
+  GAUDI_ENGINE_ID_NIC_0,
+  GAUDI_ENGINE_ID_NIC_1,
+  GAUDI_ENGINE_ID_NIC_2,
+  GAUDI_ENGINE_ID_NIC_3,
+  GAUDI_ENGINE_ID_NIC_4,
+  GAUDI_ENGINE_ID_NIC_5,
+  GAUDI_ENGINE_ID_NIC_6,
+  GAUDI_ENGINE_ID_NIC_7,
+  GAUDI_ENGINE_ID_NIC_8,
+  GAUDI_ENGINE_ID_NIC_9,
+  GAUDI_ENGINE_ID_SIZE
+};
+enum gaudi2_engine_id {
+  GAUDI2_DCORE0_ENGINE_ID_EDMA_0 = 0,
+  GAUDI2_DCORE0_ENGINE_ID_EDMA_1,
+  GAUDI2_DCORE0_ENGINE_ID_MME,
+  GAUDI2_DCORE0_ENGINE_ID_TPC_0,
+  GAUDI2_DCORE0_ENGINE_ID_TPC_1,
+  GAUDI2_DCORE0_ENGINE_ID_TPC_2,
+  GAUDI2_DCORE0_ENGINE_ID_TPC_3,
+  GAUDI2_DCORE0_ENGINE_ID_TPC_4,
+  GAUDI2_DCORE0_ENGINE_ID_TPC_5,
+  GAUDI2_DCORE0_ENGINE_ID_DEC_0,
+  GAUDI2_DCORE0_ENGINE_ID_DEC_1,
+  GAUDI2_DCORE1_ENGINE_ID_EDMA_0,
+  GAUDI2_DCORE1_ENGINE_ID_EDMA_1,
+  GAUDI2_DCORE1_ENGINE_ID_MME,
+  GAUDI2_DCORE1_ENGINE_ID_TPC_0,
+  GAUDI2_DCORE1_ENGINE_ID_TPC_1,
+  GAUDI2_DCORE1_ENGINE_ID_TPC_2,
+  GAUDI2_DCORE1_ENGINE_ID_TPC_3,
+  GAUDI2_DCORE1_ENGINE_ID_TPC_4,
+  GAUDI2_DCORE1_ENGINE_ID_TPC_5,
+  GAUDI2_DCORE1_ENGINE_ID_DEC_0,
+  GAUDI2_DCORE1_ENGINE_ID_DEC_1,
+  GAUDI2_DCORE2_ENGINE_ID_EDMA_0,
+  GAUDI2_DCORE2_ENGINE_ID_EDMA_1,
+  GAUDI2_DCORE2_ENGINE_ID_MME,
+  GAUDI2_DCORE2_ENGINE_ID_TPC_0,
+  GAUDI2_DCORE2_ENGINE_ID_TPC_1,
+  GAUDI2_DCORE2_ENGINE_ID_TPC_2,
+  GAUDI2_DCORE2_ENGINE_ID_TPC_3,
+  GAUDI2_DCORE2_ENGINE_ID_TPC_4,
+  GAUDI2_DCORE2_ENGINE_ID_TPC_5,
+  GAUDI2_DCORE2_ENGINE_ID_DEC_0,
+  GAUDI2_DCORE2_ENGINE_ID_DEC_1,
+  GAUDI2_DCORE3_ENGINE_ID_EDMA_0,
+  GAUDI2_DCORE3_ENGINE_ID_EDMA_1,
+  GAUDI2_DCORE3_ENGINE_ID_MME,
+  GAUDI2_DCORE3_ENGINE_ID_TPC_0,
+  GAUDI2_DCORE3_ENGINE_ID_TPC_1,
+  GAUDI2_DCORE3_ENGINE_ID_TPC_2,
+  GAUDI2_DCORE3_ENGINE_ID_TPC_3,
+  GAUDI2_DCORE3_ENGINE_ID_TPC_4,
+  GAUDI2_DCORE3_ENGINE_ID_TPC_5,
+  GAUDI2_DCORE3_ENGINE_ID_DEC_0,
+  GAUDI2_DCORE3_ENGINE_ID_DEC_1,
+  GAUDI2_DCORE0_ENGINE_ID_TPC_6,
+  GAUDI2_ENGINE_ID_PDMA_0,
+  GAUDI2_ENGINE_ID_PDMA_1,
+  GAUDI2_ENGINE_ID_ROT_0,
+  GAUDI2_ENGINE_ID_ROT_1,
+  GAUDI2_PCIE_ENGINE_ID_DEC_0,
+  GAUDI2_PCIE_ENGINE_ID_DEC_1,
+  GAUDI2_ENGINE_ID_NIC0_0,
+  GAUDI2_ENGINE_ID_NIC0_1,
+  GAUDI2_ENGINE_ID_NIC1_0,
+  GAUDI2_ENGINE_ID_NIC1_1,
+  GAUDI2_ENGINE_ID_NIC2_0,
+  GAUDI2_ENGINE_ID_NIC2_1,
+  GAUDI2_ENGINE_ID_NIC3_0,
+  GAUDI2_ENGINE_ID_NIC3_1,
+  GAUDI2_ENGINE_ID_NIC4_0,
+  GAUDI2_ENGINE_ID_NIC4_1,
+  GAUDI2_ENGINE_ID_NIC5_0,
+  GAUDI2_ENGINE_ID_NIC5_1,
+  GAUDI2_ENGINE_ID_NIC6_0,
+  GAUDI2_ENGINE_ID_NIC6_1,
+  GAUDI2_ENGINE_ID_NIC7_0,
+  GAUDI2_ENGINE_ID_NIC7_1,
+  GAUDI2_ENGINE_ID_NIC8_0,
+  GAUDI2_ENGINE_ID_NIC8_1,
+  GAUDI2_ENGINE_ID_NIC9_0,
+  GAUDI2_ENGINE_ID_NIC9_1,
+  GAUDI2_ENGINE_ID_NIC10_0,
+  GAUDI2_ENGINE_ID_NIC10_1,
+  GAUDI2_ENGINE_ID_NIC11_0,
+  GAUDI2_ENGINE_ID_NIC11_1,
+  GAUDI2_ENGINE_ID_PCIE,
+  GAUDI2_ENGINE_ID_PSOC,
+  GAUDI2_ENGINE_ID_ARC_FARM,
+  GAUDI2_ENGINE_ID_KDMA,
+  GAUDI2_ENGINE_ID_SIZE
+};
+enum hl_goya_pll_index {
+  HL_GOYA_CPU_PLL = 0,
+  HL_GOYA_IC_PLL,
+  HL_GOYA_MC_PLL,
+  HL_GOYA_MME_PLL,
+  HL_GOYA_PCI_PLL,
+  HL_GOYA_EMMC_PLL,
+  HL_GOYA_TPC_PLL,
+  HL_GOYA_PLL_MAX
+};
+enum hl_gaudi_pll_index {
+  HL_GAUDI_CPU_PLL = 0,
+  HL_GAUDI_PCI_PLL,
+  HL_GAUDI_SRAM_PLL,
+  HL_GAUDI_HBM_PLL,
+  HL_GAUDI_NIC_PLL,
+  HL_GAUDI_DMA_PLL,
+  HL_GAUDI_MESH_PLL,
+  HL_GAUDI_MME_PLL,
+  HL_GAUDI_TPC_PLL,
+  HL_GAUDI_IF_PLL,
+  HL_GAUDI_PLL_MAX
+};
+enum hl_gaudi2_pll_index {
+  HL_GAUDI2_CPU_PLL = 0,
+  HL_GAUDI2_PCI_PLL,
+  HL_GAUDI2_SRAM_PLL,
+  HL_GAUDI2_HBM_PLL,
+  HL_GAUDI2_NIC_PLL,
+  HL_GAUDI2_DMA_PLL,
+  HL_GAUDI2_MESH_PLL,
+  HL_GAUDI2_MME_PLL,
+  HL_GAUDI2_TPC_PLL,
+  HL_GAUDI2_IF_PLL,
+  HL_GAUDI2_VID_PLL,
+  HL_GAUDI2_MSS_PLL,
+  HL_GAUDI2_PLL_MAX
+};
+enum hl_goya_dma_direction {
+  HL_DMA_HOST_TO_DRAM,
+  HL_DMA_HOST_TO_SRAM,
+  HL_DMA_DRAM_TO_SRAM,
+  HL_DMA_SRAM_TO_DRAM,
+  HL_DMA_SRAM_TO_HOST,
+  HL_DMA_DRAM_TO_HOST,
+  HL_DMA_DRAM_TO_DRAM,
+  HL_DMA_SRAM_TO_SRAM,
+  HL_DMA_ENUM_MAX
+};
+enum hl_device_status {
+  HL_DEVICE_STATUS_OPERATIONAL,
+  HL_DEVICE_STATUS_IN_RESET,
+  HL_DEVICE_STATUS_MALFUNCTION,
+  HL_DEVICE_STATUS_NEEDS_RESET,
+  HL_DEVICE_STATUS_IN_DEVICE_CREATION,
+  HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE,
+  HL_DEVICE_STATUS_LAST = HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE
+};
+enum hl_server_type {
+  HL_SERVER_TYPE_UNKNOWN = 0,
+  HL_SERVER_GAUDI_HLS1 = 1,
+  HL_SERVER_GAUDI_HLS1H = 2,
+  HL_SERVER_GAUDI_TYPE1 = 3,
+  HL_SERVER_GAUDI_TYPE2 = 4,
+  HL_SERVER_GAUDI2_HLS2 = 5
+};
+#define HL_NOTIFIER_EVENT_TPC_ASSERT (1ULL << 0)
+#define HL_NOTIFIER_EVENT_UNDEFINED_OPCODE (1ULL << 1)
+#define HL_NOTIFIER_EVENT_DEVICE_RESET (1ULL << 2)
+#define HL_NOTIFIER_EVENT_CS_TIMEOUT (1ULL << 3)
+#define HL_NOTIFIER_EVENT_DEVICE_UNAVAILABLE (1ULL << 4)
+#define HL_NOTIFIER_EVENT_USER_ENGINE_ERR (1ULL << 5)
+#define HL_NOTIFIER_EVENT_GENERAL_HW_ERR (1ULL << 6)
+#define HL_NOTIFIER_EVENT_RAZWI (1ULL << 7)
+#define HL_NOTIFIER_EVENT_PAGE_FAULT (1ULL << 8)
+#define HL_INFO_HW_IP_INFO 0
+#define HL_INFO_HW_EVENTS 1
+#define HL_INFO_DRAM_USAGE 2
+#define HL_INFO_HW_IDLE 3
+#define HL_INFO_DEVICE_STATUS 4
+#define HL_INFO_DEVICE_UTILIZATION 6
+#define HL_INFO_HW_EVENTS_AGGREGATE 7
+#define HL_INFO_CLK_RATE 8
+#define HL_INFO_RESET_COUNT 9
+#define HL_INFO_TIME_SYNC 10
+#define HL_INFO_CS_COUNTERS 11
+#define HL_INFO_PCI_COUNTERS 12
+#define HL_INFO_CLK_THROTTLE_REASON 13
+#define HL_INFO_SYNC_MANAGER 14
+#define HL_INFO_TOTAL_ENERGY 15
+#define HL_INFO_PLL_FREQUENCY 16
+#define HL_INFO_POWER 17
+#define HL_INFO_OPEN_STATS 18
+#define HL_INFO_DRAM_REPLACED_ROWS 21
+#define HL_INFO_DRAM_PENDING_ROWS 22
+#define HL_INFO_LAST_ERR_OPEN_DEV_TIME 23
+#define HL_INFO_CS_TIMEOUT_EVENT 24
+#define HL_INFO_RAZWI_EVENT 25
+#define HL_INFO_DEV_MEM_ALLOC_PAGE_SIZES 26
+#define HL_INFO_SECURED_ATTESTATION 27
+#define HL_INFO_REGISTER_EVENTFD 28
+#define HL_INFO_UNREGISTER_EVENTFD 29
+#define HL_INFO_GET_EVENTS 30
+#define HL_INFO_UNDEFINED_OPCODE_EVENT 31
+#define HL_INFO_ENGINE_STATUS 32
+#define HL_INFO_PAGE_FAULT_EVENT 33
+#define HL_INFO_USER_MAPPINGS 34
+#define HL_INFO_FW_GENERIC_REQ 35
+#define HL_INFO_VERSION_MAX_LEN 128
+#define HL_INFO_CARD_NAME_MAX_LEN 16
+#define HL_ENGINES_DATA_MAX_SIZE SZ_1M
+struct hl_info_hw_ip_info {
+  __u64 sram_base_address;
+  __u64 dram_base_address;
+  __u64 dram_size;
+  __u32 sram_size;
+  __u32 num_of_events;
+  __u32 device_id;
+  __u32 module_id;
+  __u32 decoder_enabled_mask;
+  __u16 first_available_interrupt_id;
+  __u16 server_type;
+  __u32 cpld_version;
+  __u32 psoc_pci_pll_nr;
+  __u32 psoc_pci_pll_nf;
+  __u32 psoc_pci_pll_od;
+  __u32 psoc_pci_pll_div_factor;
+  __u8 tpc_enabled_mask;
+  __u8 dram_enabled;
+  __u8 security_enabled;
+  __u8 mme_master_slave_mode;
+  __u8 cpucp_version[HL_INFO_VERSION_MAX_LEN];
+  __u8 card_name[HL_INFO_CARD_NAME_MAX_LEN];
+  __u64 tpc_enabled_mask_ext;
+  __u64 dram_page_size;
+  __u32 edma_enabled_mask;
+  __u16 number_of_user_interrupts;
+  __u16 pad2;
+  __u64 reserved4;
+  __u64 device_mem_alloc_default_page_size;
+  __u64 reserved5;
+  __u64 reserved6;
+  __u32 reserved7;
+  __u8 reserved8;
+  __u8 revision_id;
+  __u8 pad[2];
+};
+struct hl_info_dram_usage {
+  __u64 dram_free_mem;
+  __u64 ctx_dram_mem;
+};
+#define HL_BUSY_ENGINES_MASK_EXT_SIZE 4
+struct hl_info_hw_idle {
+  __u32 is_idle;
+  __u32 busy_engines_mask;
+  __u64 busy_engines_mask_ext[HL_BUSY_ENGINES_MASK_EXT_SIZE];
+};
+struct hl_info_device_status {
+  __u32 status;
+  __u32 pad;
+};
+struct hl_info_device_utilization {
+  __u32 utilization;
+  __u32 pad;
+};
+struct hl_info_clk_rate {
+  __u32 cur_clk_rate_mhz;
+  __u32 max_clk_rate_mhz;
+};
+struct hl_info_reset_count {
+  __u32 hard_reset_cnt;
+  __u32 soft_reset_cnt;
+};
+struct hl_info_time_sync {
+  __u64 device_time;
+  __u64 host_time;
+};
+struct hl_info_pci_counters {
+  __u64 rx_throughput;
+  __u64 tx_throughput;
+  __u64 replay_cnt;
+};
+enum hl_clk_throttling_type {
+  HL_CLK_THROTTLE_TYPE_POWER,
+  HL_CLK_THROTTLE_TYPE_THERMAL,
+  HL_CLK_THROTTLE_TYPE_MAX
+};
+#define HL_CLK_THROTTLE_POWER (1 << HL_CLK_THROTTLE_TYPE_POWER)
+#define HL_CLK_THROTTLE_THERMAL (1 << HL_CLK_THROTTLE_TYPE_THERMAL)
+struct hl_info_clk_throttle {
+  __u32 clk_throttling_reason;
+  __u32 pad;
+  __u64 clk_throttling_timestamp_us[HL_CLK_THROTTLE_TYPE_MAX];
+  __u64 clk_throttling_duration_ns[HL_CLK_THROTTLE_TYPE_MAX];
+};
+struct hl_info_energy {
+  __u64 total_energy_consumption;
+};
+#define HL_PLL_NUM_OUTPUTS 4
+struct hl_pll_frequency_info {
+  __u16 output[HL_PLL_NUM_OUTPUTS];
+};
+struct hl_open_stats_info {
+  __u64 open_counter;
+  __u64 last_open_period_ms;
+  __u8 is_compute_ctx_active;
+  __u8 compute_ctx_in_release;
+  __u8 pad[6];
+};
+struct hl_power_info {
+  __u64 power;
+};
+struct hl_info_sync_manager {
+  __u32 first_available_sync_object;
+  __u32 first_available_monitor;
+  __u32 first_available_cq;
+  __u32 reserved;
+};
+struct hl_info_cs_counters {
+  __u64 total_out_of_mem_drop_cnt;
+  __u64 ctx_out_of_mem_drop_cnt;
+  __u64 total_parsing_drop_cnt;
+  __u64 ctx_parsing_drop_cnt;
+  __u64 total_queue_full_drop_cnt;
+  __u64 ctx_queue_full_drop_cnt;
+  __u64 total_device_in_reset_drop_cnt;
+  __u64 ctx_device_in_reset_drop_cnt;
+  __u64 total_max_cs_in_flight_drop_cnt;
+  __u64 ctx_max_cs_in_flight_drop_cnt;
+  __u64 total_validation_drop_cnt;
+  __u64 ctx_validation_drop_cnt;
+};
+struct hl_info_last_err_open_dev_time {
+  __s64 timestamp;
+};
+struct hl_info_cs_timeout_event {
+  __s64 timestamp;
+  __u64 seq;
+};
+#define HL_RAZWI_NA_ENG_ID U16_MAX
+#define HL_RAZWI_MAX_NUM_OF_ENGINES_PER_RTR 128
+#define HL_RAZWI_READ BIT(0)
+#define HL_RAZWI_WRITE BIT(1)
+#define HL_RAZWI_LBW BIT(2)
+#define HL_RAZWI_HBW BIT(3)
+#define HL_RAZWI_RR BIT(4)
+#define HL_RAZWI_ADDR_DEC BIT(5)
+struct hl_info_razwi_event {
+  __s64 timestamp;
+  __u64 addr;
+  __u16 engine_id[HL_RAZWI_MAX_NUM_OF_ENGINES_PER_RTR];
+  __u16 num_of_possible_engines;
+  __u8 flags;
+  __u8 pad[5];
+};
+#define MAX_QMAN_STREAMS_INFO 4
+#define OPCODE_INFO_MAX_ADDR_SIZE 8
+struct hl_info_undefined_opcode_event {
+  __s64 timestamp;
+  __u64 cb_addr_streams[MAX_QMAN_STREAMS_INFO][OPCODE_INFO_MAX_ADDR_SIZE];
+  __u64 cq_addr;
+  __u32 cq_size;
+  __u32 cb_addr_streams_len;
+  __u32 engine_id;
+  __u32 stream_id;
+};
+struct hl_info_dev_memalloc_page_sizes {
+  __u64 page_order_bitmask;
+};
+#define SEC_PCR_DATA_BUF_SZ 256
+#define SEC_PCR_QUOTE_BUF_SZ 510
+#define SEC_SIGNATURE_BUF_SZ 255
+#define SEC_PUB_DATA_BUF_SZ 510
+#define SEC_CERTIFICATE_BUF_SZ 2046
+struct hl_info_sec_attest {
+  __u32 nonce;
+  __u16 pcr_quote_len;
+  __u16 pub_data_len;
+  __u16 certificate_len;
+  __u8 pcr_num_reg;
+  __u8 pcr_reg_len;
+  __u8 quote_sig_len;
+  __u8 pcr_data[SEC_PCR_DATA_BUF_SZ];
+  __u8 pcr_quote[SEC_PCR_QUOTE_BUF_SZ];
+  __u8 quote_sig[SEC_SIGNATURE_BUF_SZ];
+  __u8 public_data[SEC_PUB_DATA_BUF_SZ];
+  __u8 certificate[SEC_CERTIFICATE_BUF_SZ];
+  __u8 pad0[2];
+};
+struct hl_page_fault_info {
+  __s64 timestamp;
+  __u64 addr;
+  __u16 engine_id;
+  __u8 pad[6];
+};
+struct hl_user_mapping {
+  __u64 dev_va;
+  __u64 size;
+};
+enum gaudi_dcores {
+  HL_GAUDI_WS_DCORE,
+  HL_GAUDI_WN_DCORE,
+  HL_GAUDI_EN_DCORE,
+  HL_GAUDI_ES_DCORE
+};
+struct hl_info_args {
+  __u64 return_pointer;
+  __u32 return_size;
+  __u32 op;
+  union {
+    __u32 dcore_id;
+    __u32 ctx_id;
+    __u32 period_ms;
+    __u32 pll_index;
+    __u32 eventfd;
+    __u32 user_buffer_actual_size;
+    __u32 sec_attest_nonce;
+    __u32 array_size;
+    __u32 fw_sub_opcode;
+  };
+  __u32 pad;
+};
+#define HL_CB_OP_CREATE 0
+#define HL_CB_OP_DESTROY 1
+#define HL_CB_OP_INFO 2
+#define HL_MAX_CB_SIZE (0x200000 - 32)
+#define HL_CB_FLAGS_MAP 0x1
+#define HL_CB_FLAGS_GET_DEVICE_VA 0x2
+struct hl_cb_in {
+  __u64 cb_handle;
+  __u32 op;
+  __u32 cb_size;
+  __u32 ctx_id;
+  __u32 flags;
+};
+struct hl_cb_out {
+  union {
+    __u64 cb_handle;
+    union {
+      struct {
+        __u32 usage_cnt;
+        __u32 pad;
+      };
+      __u64 device_va;
+    };
+  };
+};
+union hl_cb_args {
+  struct hl_cb_in in;
+  struct hl_cb_out out;
+};
+#define HL_CS_CHUNK_FLAGS_USER_ALLOC_CB 0x1
+struct hl_cs_chunk {
+  union {
+    __u64 cb_handle;
+    __u64 signal_seq_arr;
+    __u64 encaps_signal_seq;
+  };
+  __u32 queue_index;
+  union {
+    __u32 cb_size;
+    __u32 num_signal_seq_arr;
+    __u32 encaps_signal_offset;
+  };
+  __u32 cs_chunk_flags;
+  __u32 collective_engine_id;
+  __u32 pad[10];
+};
+#define HL_CS_FLAGS_FORCE_RESTORE 0x1
+#define HL_CS_FLAGS_SIGNAL 0x2
+#define HL_CS_FLAGS_WAIT 0x4
+#define HL_CS_FLAGS_COLLECTIVE_WAIT 0x8
+#define HL_CS_FLAGS_TIMESTAMP 0x20
+#define HL_CS_FLAGS_STAGED_SUBMISSION 0x40
+#define HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 0x80
+#define HL_CS_FLAGS_STAGED_SUBMISSION_LAST 0x100
+#define HL_CS_FLAGS_CUSTOM_TIMEOUT 0x200
+#define HL_CS_FLAGS_SKIP_RESET_ON_TIMEOUT 0x400
+#define HL_CS_FLAGS_ENCAP_SIGNALS 0x800
+#define HL_CS_FLAGS_RESERVE_SIGNALS_ONLY 0x1000
+#define HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY 0x2000
+#define HL_CS_FLAGS_ENGINE_CORE_COMMAND 0x4000
+#define HL_CS_FLAGS_FLUSH_PCI_HBW_WRITES 0x8000
+#define HL_CS_STATUS_SUCCESS 0
+#define HL_MAX_JOBS_PER_CS 512
+#define HL_ENGINE_CORE_HALT (1 << 0)
+#define HL_ENGINE_CORE_RUN (1 << 1)
+struct hl_cs_in {
+  union {
+    struct {
+      __u64 chunks_restore;
+      __u64 chunks_execute;
+    };
+    struct {
+      __u64 engine_cores;
+      __u32 num_engine_cores;
+      __u32 core_command;
+    };
+  };
+  union {
+    __u64 seq;
+    __u32 encaps_sig_handle_id;
+    struct {
+      __u32 encaps_signals_count;
+      __u32 encaps_signals_q_idx;
+    };
+  };
+  __u32 num_chunks_restore;
+  __u32 num_chunks_execute;
+  __u32 timeout;
+  __u32 cs_flags;
+  __u32 ctx_id;
+  __u8 pad[4];
+};
+struct hl_cs_out {
+  union {
+    __u64 seq;
+    struct {
+      __u32 handle_id;
+      __u32 count;
+    };
+  };
+  __u32 status;
+  __u32 sob_base_addr_offset;
+  __u16 sob_count_before_submission;
+  __u16 pad[3];
+};
+union hl_cs_args {
+  struct hl_cs_in in;
+  struct hl_cs_out out;
+};
+#define HL_WAIT_CS_FLAGS_INTERRUPT 0x2
+#define HL_WAIT_CS_FLAGS_INTERRUPT_MASK 0xFFF00000
+#define HL_WAIT_CS_FLAGS_ANY_CQ_INTERRUPT 0xFFF00000
+#define HL_WAIT_CS_FLAGS_ANY_DEC_INTERRUPT 0xFFE00000
+#define HL_WAIT_CS_FLAGS_MULTI_CS 0x4
+#define HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ 0x10
+#define HL_WAIT_CS_FLAGS_REGISTER_INTERRUPT 0x20
+#define HL_WAIT_MULTI_CS_LIST_MAX_LEN 32
+struct hl_wait_cs_in {
+  union {
+    struct {
+      __u64 seq;
+      __u64 timeout_us;
+    };
+    struct {
+      union {
+        __u64 addr;
+        __u64 cq_counters_handle;
+      };
+      __u64 target;
+    };
+  };
+  __u32 ctx_id;
+  __u32 flags;
+  union {
+    struct {
+      __u8 seq_arr_len;
+      __u8 pad[7];
+    };
+    __u64 interrupt_timeout_us;
+  };
+  __u64 cq_counters_offset;
+  __u64 timestamp_handle;
+  __u64 timestamp_offset;
+};
+#define HL_WAIT_CS_STATUS_COMPLETED 0
+#define HL_WAIT_CS_STATUS_BUSY 1
+#define HL_WAIT_CS_STATUS_TIMEDOUT 2
+#define HL_WAIT_CS_STATUS_ABORTED 3
+#define HL_WAIT_CS_STATUS_FLAG_GONE 0x1
+#define HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD 0x2
+struct hl_wait_cs_out {
+  __u32 status;
+  __u32 flags;
+  __s64 timestamp_nsec;
+  __u32 cs_completion_map;
+  __u32 pad;
+};
+union hl_wait_cs_args {
+  struct hl_wait_cs_in in;
+  struct hl_wait_cs_out out;
+};
+#define HL_MEM_OP_ALLOC 0
+#define HL_MEM_OP_FREE 1
+#define HL_MEM_OP_MAP 2
+#define HL_MEM_OP_UNMAP 3
+#define HL_MEM_OP_MAP_BLOCK 4
+#define HL_MEM_OP_EXPORT_DMABUF_FD 5
+#define HL_MEM_OP_TS_ALLOC 6
+#define HL_MEM_CONTIGUOUS 0x1
+#define HL_MEM_SHARED 0x2
+#define HL_MEM_USERPTR 0x4
+#define HL_MEM_FORCE_HINT 0x8
+#define HL_MEM_PREFETCH 0x40
+struct hl_mem_in {
+  union {
+    struct {
+      __u64 mem_size;
+      __u64 page_size;
+    } alloc;
+    struct {
+      __u64 handle;
+    } free;
+    struct {
+      __u64 hint_addr;
+      __u64 handle;
+    } map_device;
+    struct {
+      __u64 host_virt_addr;
+      __u64 hint_addr;
+      __u64 mem_size;
+    } map_host;
+    struct {
+      __u64 block_addr;
+    } map_block;
+    struct {
+      __u64 device_virt_addr;
+    } unmap;
+    struct {
+      __u64 addr;
+      __u64 mem_size;
+      __u64 offset;
+    } export_dmabuf_fd;
+  };
+  __u32 op;
+  __u32 flags;
+  __u32 ctx_id;
+  __u32 num_of_elements;
+};
+struct hl_mem_out {
+  union {
+    __u64 device_virt_addr;
+    __u64 handle;
+    struct {
+      __u64 block_handle;
+      __u32 block_size;
+      __u32 pad;
+    };
+    __s32 fd;
+  };
+};
+union hl_mem_args {
+  struct hl_mem_in in;
+  struct hl_mem_out out;
+};
+#define HL_DEBUG_MAX_AUX_VALUES 10
+struct hl_debug_params_etr {
+  __u64 buffer_address;
+  __u64 buffer_size;
+  __u32 sink_mode;
+  __u32 pad;
+};
+struct hl_debug_params_etf {
+  __u64 buffer_address;
+  __u64 buffer_size;
+  __u32 sink_mode;
+  __u32 pad;
+};
+struct hl_debug_params_stm {
+  __u64 he_mask;
+  __u64 sp_mask;
+  __u32 id;
+  __u32 frequency;
+};
+struct hl_debug_params_bmon {
+  __u64 start_addr0;
+  __u64 addr_mask0;
+  __u64 start_addr1;
+  __u64 addr_mask1;
+  __u32 bw_win;
+  __u32 win_capture;
+  __u32 id;
+  __u32 control;
+  __u64 start_addr2;
+  __u64 end_addr2;
+  __u64 start_addr3;
+  __u64 end_addr3;
+};
+struct hl_debug_params_spmu {
+  __u64 event_types[HL_DEBUG_MAX_AUX_VALUES];
+  __u32 event_types_num;
+  __u32 pmtrc_val;
+  __u32 trc_ctrl_host_val;
+  __u32 trc_en_host_val;
+};
+#define HL_DEBUG_OP_ETR 0
+#define HL_DEBUG_OP_ETF 1
+#define HL_DEBUG_OP_STM 2
+#define HL_DEBUG_OP_FUNNEL 3
+#define HL_DEBUG_OP_BMON 4
+#define HL_DEBUG_OP_SPMU 5
+#define HL_DEBUG_OP_TIMESTAMP 6
+#define HL_DEBUG_OP_SET_MODE 7
+struct hl_debug_args {
+  __u64 input_ptr;
+  __u64 output_ptr;
+  __u32 input_size;
+  __u32 output_size;
+  __u32 op;
+  __u32 reg_idx;
+  __u32 enable;
+  __u32 ctx_id;
+};
+#define HL_IOCTL_INFO _IOWR('H', 0x01, struct hl_info_args)
+#define HL_IOCTL_CB _IOWR('H', 0x02, union hl_cb_args)
+#define HL_IOCTL_CS _IOWR('H', 0x03, union hl_cs_args)
+#define HL_IOCTL_WAIT_CS _IOWR('H', 0x04, union hl_wait_cs_args)
+#define HL_IOCTL_MEMORY _IOWR('H', 0x05, union hl_mem_args)
+#define HL_IOCTL_DEBUG _IOWR('H', 0x06, struct hl_debug_args)
+#define HL_COMMAND_START 0x01
+#define HL_COMMAND_END 0x07
+#endif
diff --git a/libc/kernel/uapi/drm/i810_drm.h b/libc/kernel/uapi/drm/i810_drm.h
deleted file mode 100644
index e33387d..0000000
--- a/libc/kernel/uapi/drm/i810_drm.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/****************************************************************************
- ****************************************************************************
- ***
- ***   This header was automatically generated from a Linux kernel header
- ***   of the same name, to make information necessary for userspace to
- ***   call into the kernel available to libc.  It contains only constants,
- ***   structures, and macros generated from the original header, and thus,
- ***   contains no copyrightable information.
- ***
- ***   To edit the content of this header, modify the corresponding
- ***   source file (e.g. under external/kernel-headers/original/) then
- ***   run bionic/libc/kernel/tools/update_all.py
- ***
- ***   Any manual change here will be lost the next time this script will
- ***   be run. You've been warned!
- ***
- ****************************************************************************
- ****************************************************************************/
-#ifndef _I810_DRM_H_
-#define _I810_DRM_H_
-#include "drm.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-#ifndef _I810_DEFINES_
-#define _I810_DEFINES_
-#define I810_DMA_BUF_ORDER 12
-#define I810_DMA_BUF_SZ (1 << I810_DMA_BUF_ORDER)
-#define I810_DMA_BUF_NR 256
-#define I810_NR_SAREA_CLIPRECTS 8
-#define I810_NR_TEX_REGIONS 64
-#define I810_LOG_MIN_TEX_REGION_SIZE 16
-#endif
-#define I810_UPLOAD_TEX0IMAGE 0x1
-#define I810_UPLOAD_TEX1IMAGE 0x2
-#define I810_UPLOAD_CTX 0x4
-#define I810_UPLOAD_BUFFERS 0x8
-#define I810_UPLOAD_TEX0 0x10
-#define I810_UPLOAD_TEX1 0x20
-#define I810_UPLOAD_CLIPRECTS 0x40
-#define I810_DESTREG_DI0 0
-#define I810_DESTREG_DI1 1
-#define I810_DESTREG_DV0 2
-#define I810_DESTREG_DV1 3
-#define I810_DESTREG_DR0 4
-#define I810_DESTREG_DR1 5
-#define I810_DESTREG_DR2 6
-#define I810_DESTREG_DR3 7
-#define I810_DESTREG_DR4 8
-#define I810_DEST_SETUP_SIZE 10
-#define I810_CTXREG_CF0 0
-#define I810_CTXREG_CF1 1
-#define I810_CTXREG_ST0 2
-#define I810_CTXREG_ST1 3
-#define I810_CTXREG_VF 4
-#define I810_CTXREG_MT 5
-#define I810_CTXREG_MC0 6
-#define I810_CTXREG_MC1 7
-#define I810_CTXREG_MC2 8
-#define I810_CTXREG_MA0 9
-#define I810_CTXREG_MA1 10
-#define I810_CTXREG_MA2 11
-#define I810_CTXREG_SDM 12
-#define I810_CTXREG_FOG 13
-#define I810_CTXREG_B1 14
-#define I810_CTXREG_B2 15
-#define I810_CTXREG_LCS 16
-#define I810_CTXREG_PV 17
-#define I810_CTXREG_ZA 18
-#define I810_CTXREG_AA 19
-#define I810_CTX_SETUP_SIZE 20
-#define I810_TEXREG_MI0 0
-#define I810_TEXREG_MI1 1
-#define I810_TEXREG_MI2 2
-#define I810_TEXREG_MI3 3
-#define I810_TEXREG_MF 4
-#define I810_TEXREG_MLC 5
-#define I810_TEXREG_MLL 6
-#define I810_TEXREG_MCS 7
-#define I810_TEX_SETUP_SIZE 8
-#define I810_FRONT 0x1
-#define I810_BACK 0x2
-#define I810_DEPTH 0x4
-typedef enum _drm_i810_init_func {
-  I810_INIT_DMA = 0x01,
-  I810_CLEANUP_DMA = 0x02,
-  I810_INIT_DMA_1_4 = 0x03
-} drm_i810_init_func_t;
-typedef struct _drm_i810_init {
-  drm_i810_init_func_t func;
-  unsigned int mmio_offset;
-  unsigned int buffers_offset;
-  int sarea_priv_offset;
-  unsigned int ring_start;
-  unsigned int ring_end;
-  unsigned int ring_size;
-  unsigned int front_offset;
-  unsigned int back_offset;
-  unsigned int depth_offset;
-  unsigned int overlay_offset;
-  unsigned int overlay_physical;
-  unsigned int w;
-  unsigned int h;
-  unsigned int pitch;
-  unsigned int pitch_bits;
-} drm_i810_init_t;
-typedef struct _drm_i810_pre12_init {
-  drm_i810_init_func_t func;
-  unsigned int mmio_offset;
-  unsigned int buffers_offset;
-  int sarea_priv_offset;
-  unsigned int ring_start;
-  unsigned int ring_end;
-  unsigned int ring_size;
-  unsigned int front_offset;
-  unsigned int back_offset;
-  unsigned int depth_offset;
-  unsigned int w;
-  unsigned int h;
-  unsigned int pitch;
-  unsigned int pitch_bits;
-} drm_i810_pre12_init_t;
-typedef struct _drm_i810_tex_region {
-  unsigned char next, prev;
-  unsigned char in_use;
-  int age;
-} drm_i810_tex_region_t;
-typedef struct _drm_i810_sarea {
-  unsigned int ContextState[I810_CTX_SETUP_SIZE];
-  unsigned int BufferState[I810_DEST_SETUP_SIZE];
-  unsigned int TexState[2][I810_TEX_SETUP_SIZE];
-  unsigned int dirty;
-  unsigned int nbox;
-  struct drm_clip_rect boxes[I810_NR_SAREA_CLIPRECTS];
-  drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS + 1];
-  int texAge;
-  int last_enqueue;
-  int last_dispatch;
-  int last_quiescent;
-  int ctxOwner;
-  int vertex_prim;
-  int pf_enabled;
-  int pf_active;
-  int pf_current_page;
-} drm_i810_sarea_t;
-#define DRM_I810_INIT 0x00
-#define DRM_I810_VERTEX 0x01
-#define DRM_I810_CLEAR 0x02
-#define DRM_I810_FLUSH 0x03
-#define DRM_I810_GETAGE 0x04
-#define DRM_I810_GETBUF 0x05
-#define DRM_I810_SWAP 0x06
-#define DRM_I810_COPY 0x07
-#define DRM_I810_DOCOPY 0x08
-#define DRM_I810_OV0INFO 0x09
-#define DRM_I810_FSTATUS 0x0a
-#define DRM_I810_OV0FLIP 0x0b
-#define DRM_I810_MC 0x0c
-#define DRM_I810_RSTATUS 0x0d
-#define DRM_I810_FLIP 0x0e
-#define DRM_IOCTL_I810_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I810_INIT, drm_i810_init_t)
-#define DRM_IOCTL_I810_VERTEX DRM_IOW(DRM_COMMAND_BASE + DRM_I810_VERTEX, drm_i810_vertex_t)
-#define DRM_IOCTL_I810_CLEAR DRM_IOW(DRM_COMMAND_BASE + DRM_I810_CLEAR, drm_i810_clear_t)
-#define DRM_IOCTL_I810_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_I810_FLUSH)
-#define DRM_IOCTL_I810_GETAGE DRM_IO(DRM_COMMAND_BASE + DRM_I810_GETAGE)
-#define DRM_IOCTL_I810_GETBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_I810_GETBUF, drm_i810_dma_t)
-#define DRM_IOCTL_I810_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_I810_SWAP)
-#define DRM_IOCTL_I810_COPY DRM_IOW(DRM_COMMAND_BASE + DRM_I810_COPY, drm_i810_copy_t)
-#define DRM_IOCTL_I810_DOCOPY DRM_IO(DRM_COMMAND_BASE + DRM_I810_DOCOPY)
-#define DRM_IOCTL_I810_OV0INFO DRM_IOR(DRM_COMMAND_BASE + DRM_I810_OV0INFO, drm_i810_overlay_t)
-#define DRM_IOCTL_I810_FSTATUS DRM_IO(DRM_COMMAND_BASE + DRM_I810_FSTATUS)
-#define DRM_IOCTL_I810_OV0FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I810_OV0FLIP)
-#define DRM_IOCTL_I810_MC DRM_IOW(DRM_COMMAND_BASE + DRM_I810_MC, drm_i810_mc_t)
-#define DRM_IOCTL_I810_RSTATUS DRM_IO(DRM_COMMAND_BASE + DRM_I810_RSTATUS)
-#define DRM_IOCTL_I810_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I810_FLIP)
-typedef struct _drm_i810_clear {
-  int clear_color;
-  int clear_depth;
-  int flags;
-} drm_i810_clear_t;
-typedef struct _drm_i810_vertex {
-  int idx;
-  int used;
-  int discard;
-} drm_i810_vertex_t;
-typedef struct _drm_i810_copy_t {
-  int idx;
-  int used;
-  void * address;
-} drm_i810_copy_t;
-#define PR_TRIANGLES (0x0 << 18)
-#define PR_TRISTRIP_0 (0x1 << 18)
-#define PR_TRISTRIP_1 (0x2 << 18)
-#define PR_TRIFAN (0x3 << 18)
-#define PR_POLYGON (0x4 << 18)
-#define PR_LINES (0x5 << 18)
-#define PR_LINESTRIP (0x6 << 18)
-#define PR_RECTS (0x7 << 18)
-#define PR_MASK (0x7 << 18)
-typedef struct drm_i810_dma {
-  void * __linux_virtual;
-  int request_idx;
-  int request_size;
-  int granted;
-} drm_i810_dma_t;
-typedef struct _drm_i810_overlay_t {
-  unsigned int offset;
-  unsigned int physical;
-} drm_i810_overlay_t;
-typedef struct _drm_i810_mc {
-  int idx;
-  int used;
-  int num_blocks;
-  int * length;
-  unsigned int last_render;
-} drm_i810_mc_t;
-#ifdef __cplusplus
-}
-#endif
-#endif
diff --git a/libc/kernel/uapi/drm/ivpu_accel.h b/libc/kernel/uapi/drm/ivpu_accel.h
new file mode 100644
index 0000000..e148a5b
--- /dev/null
+++ b/libc/kernel/uapi/drm/ivpu_accel.h
@@ -0,0 +1,102 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ***   To edit the content of this header, modify the corresponding
+ ***   source file (e.g. under external/kernel-headers/original/) then
+ ***   run bionic/libc/kernel/tools/update_all.py
+ ***
+ ***   Any manual change here will be lost the next time this script will
+ ***   be run. You've been warned!
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef __UAPI_IVPU_DRM_H__
+#define __UAPI_IVPU_DRM_H__
+#include "drm.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+#define DRM_IVPU_DRIVER_MAJOR 1
+#define DRM_IVPU_DRIVER_MINOR 0
+#define DRM_IVPU_GET_PARAM 0x00
+#define DRM_IVPU_SET_PARAM 0x01
+#define DRM_IVPU_BO_CREATE 0x02
+#define DRM_IVPU_BO_INFO 0x03
+#define DRM_IVPU_SUBMIT 0x05
+#define DRM_IVPU_BO_WAIT 0x06
+#define DRM_IOCTL_IVPU_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_GET_PARAM, struct drm_ivpu_param)
+#define DRM_IOCTL_IVPU_SET_PARAM DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_SET_PARAM, struct drm_ivpu_param)
+#define DRM_IOCTL_IVPU_BO_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_CREATE, struct drm_ivpu_bo_create)
+#define DRM_IOCTL_IVPU_BO_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_INFO, struct drm_ivpu_bo_info)
+#define DRM_IOCTL_IVPU_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_SUBMIT, struct drm_ivpu_submit)
+#define DRM_IOCTL_IVPU_BO_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_WAIT, struct drm_ivpu_bo_wait)
+#define DRM_IVPU_PARAM_DEVICE_ID 0
+#define DRM_IVPU_PARAM_DEVICE_REVISION 1
+#define DRM_IVPU_PARAM_PLATFORM_TYPE 2
+#define DRM_IVPU_PARAM_CORE_CLOCK_RATE 3
+#define DRM_IVPU_PARAM_NUM_CONTEXTS 4
+#define DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS 5
+#define DRM_IVPU_PARAM_CONTEXT_PRIORITY 6
+#define DRM_IVPU_PARAM_CONTEXT_ID 7
+#define DRM_IVPU_PARAM_FW_API_VERSION 8
+#define DRM_IVPU_PARAM_ENGINE_HEARTBEAT 9
+#define DRM_IVPU_PARAM_UNIQUE_INFERENCE_ID 10
+#define DRM_IVPU_PARAM_TILE_CONFIG 11
+#define DRM_IVPU_PARAM_SKU 12
+#define DRM_IVPU_PLATFORM_TYPE_SILICON 0
+#define DRM_IVPU_CONTEXT_PRIORITY_IDLE 0
+#define DRM_IVPU_CONTEXT_PRIORITY_NORMAL 1
+#define DRM_IVPU_CONTEXT_PRIORITY_FOCUS 2
+#define DRM_IVPU_CONTEXT_PRIORITY_REALTIME 3
+struct drm_ivpu_param {
+  __u32 param;
+  __u32 index;
+  __u64 value;
+};
+#define DRM_IVPU_BO_HIGH_MEM 0x00000001
+#define DRM_IVPU_BO_MAPPABLE 0x00000002
+#define DRM_IVPU_BO_CACHED 0x00000000
+#define DRM_IVPU_BO_UNCACHED 0x00010000
+#define DRM_IVPU_BO_WC 0x00020000
+#define DRM_IVPU_BO_CACHE_MASK 0x00030000
+#define DRM_IVPU_BO_FLAGS (DRM_IVPU_BO_HIGH_MEM | DRM_IVPU_BO_MAPPABLE | DRM_IVPU_BO_CACHE_MASK)
+struct drm_ivpu_bo_create {
+  __u64 size;
+  __u32 flags;
+  __u32 handle;
+  __u64 vpu_addr;
+};
+struct drm_ivpu_bo_info {
+  __u32 handle;
+  __u32 flags;
+  __u64 vpu_addr;
+  __u64 mmap_offset;
+  __u64 size;
+};
+#define DRM_IVPU_ENGINE_COMPUTE 0
+#define DRM_IVPU_ENGINE_COPY 1
+struct drm_ivpu_submit {
+  __u64 buffers_ptr;
+  __u32 buffer_count;
+  __u32 engine;
+  __u32 flags;
+  __u32 commands_offset;
+};
+#define DRM_IVPU_JOB_STATUS_SUCCESS 0
+struct drm_ivpu_bo_wait {
+  __u32 handle;
+  __u32 flags;
+  __s64 timeout_ns;
+  __u32 job_status;
+  __u32 pad;
+};
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/libc/kernel/uapi/drm/mga_drm.h b/libc/kernel/uapi/drm/mga_drm.h
deleted file mode 100644
index eb55fa7..0000000
--- a/libc/kernel/uapi/drm/mga_drm.h
+++ /dev/null
@@ -1,247 +0,0 @@
-/****************************************************************************
- ****************************************************************************
- ***
- ***   This header was automatically generated from a Linux kernel header
- ***   of the same name, to make information necessary for userspace to
- ***   call into the kernel available to libc.  It contains only constants,
- ***   structures, and macros generated from the original header, and thus,
- ***   contains no copyrightable information.
- ***
- ***   To edit the content of this header, modify the corresponding
- ***   source file (e.g. under external/kernel-headers/original/) then
- ***   run bionic/libc/kernel/tools/update_all.py
- ***
- ***   Any manual change here will be lost the next time this script will
- ***   be run. You've been warned!
- ***
- ****************************************************************************
- ****************************************************************************/
-#ifndef __MGA_DRM_H__
-#define __MGA_DRM_H__
-#include "drm.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-#ifndef __MGA_SAREA_DEFINES__
-#define __MGA_SAREA_DEFINES__
-#define MGA_F 0x1
-#define MGA_A 0x2
-#define MGA_S 0x4
-#define MGA_T2 0x8
-#define MGA_WARP_TGZ 0
-#define MGA_WARP_TGZF (MGA_F)
-#define MGA_WARP_TGZA (MGA_A)
-#define MGA_WARP_TGZAF (MGA_F | MGA_A)
-#define MGA_WARP_TGZS (MGA_S)
-#define MGA_WARP_TGZSF (MGA_S | MGA_F)
-#define MGA_WARP_TGZSA (MGA_S | MGA_A)
-#define MGA_WARP_TGZSAF (MGA_S | MGA_F | MGA_A)
-#define MGA_WARP_T2GZ (MGA_T2)
-#define MGA_WARP_T2GZF (MGA_T2 | MGA_F)
-#define MGA_WARP_T2GZA (MGA_T2 | MGA_A)
-#define MGA_WARP_T2GZAF (MGA_T2 | MGA_A | MGA_F)
-#define MGA_WARP_T2GZS (MGA_T2 | MGA_S)
-#define MGA_WARP_T2GZSF (MGA_T2 | MGA_S | MGA_F)
-#define MGA_WARP_T2GZSA (MGA_T2 | MGA_S | MGA_A)
-#define MGA_WARP_T2GZSAF (MGA_T2 | MGA_S | MGA_F | MGA_A)
-#define MGA_MAX_G200_PIPES 8
-#define MGA_MAX_G400_PIPES 16
-#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES
-#define MGA_WARP_UCODE_SIZE 32768
-#define MGA_CARD_TYPE_G200 1
-#define MGA_CARD_TYPE_G400 2
-#define MGA_CARD_TYPE_G450 3
-#define MGA_CARD_TYPE_G550 4
-#define MGA_FRONT 0x1
-#define MGA_BACK 0x2
-#define MGA_DEPTH 0x4
-#define MGA_UPLOAD_CONTEXT 0x1
-#define MGA_UPLOAD_TEX0 0x2
-#define MGA_UPLOAD_TEX1 0x4
-#define MGA_UPLOAD_PIPE 0x8
-#define MGA_UPLOAD_TEX0IMAGE 0x10
-#define MGA_UPLOAD_TEX1IMAGE 0x20
-#define MGA_UPLOAD_2D 0x40
-#define MGA_WAIT_AGE 0x80
-#define MGA_UPLOAD_CLIPRECTS 0x100
-#define MGA_BUFFER_SIZE (1 << 16)
-#define MGA_NUM_BUFFERS 128
-#define MGA_NR_SAREA_CLIPRECTS 8
-#define MGA_CARD_HEAP 0
-#define MGA_AGP_HEAP 1
-#define MGA_NR_TEX_HEAPS 2
-#define MGA_NR_TEX_REGIONS 16
-#define MGA_LOG_MIN_TEX_REGION_SIZE 16
-#define DRM_MGA_IDLE_RETRY 2048
-#endif
-typedef struct {
-  unsigned int dstorg;
-  unsigned int maccess;
-  unsigned int plnwt;
-  unsigned int dwgctl;
-  unsigned int alphactrl;
-  unsigned int fogcolor;
-  unsigned int wflag;
-  unsigned int tdualstage0;
-  unsigned int tdualstage1;
-  unsigned int fcol;
-  unsigned int stencil;
-  unsigned int stencilctl;
-} drm_mga_context_regs_t;
-typedef struct {
-  unsigned int pitch;
-} drm_mga_server_regs_t;
-typedef struct {
-  unsigned int texctl;
-  unsigned int texctl2;
-  unsigned int texfilter;
-  unsigned int texbordercol;
-  unsigned int texorg;
-  unsigned int texwidth;
-  unsigned int texheight;
-  unsigned int texorg1;
-  unsigned int texorg2;
-  unsigned int texorg3;
-  unsigned int texorg4;
-} drm_mga_texture_regs_t;
-typedef struct {
-  unsigned int head;
-  unsigned int wrap;
-} drm_mga_age_t;
-typedef struct _drm_mga_sarea {
-  drm_mga_context_regs_t context_state;
-  drm_mga_server_regs_t server_state;
-  drm_mga_texture_regs_t tex_state[2];
-  unsigned int warp_pipe;
-  unsigned int dirty;
-  unsigned int vertsize;
-  struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS];
-  unsigned int nbox;
-  unsigned int req_drawable;
-  unsigned int req_draw_buffer;
-  unsigned int exported_drawable;
-  unsigned int exported_index;
-  unsigned int exported_stamp;
-  unsigned int exported_buffers;
-  unsigned int exported_nfront;
-  unsigned int exported_nback;
-  int exported_back_x, exported_front_x, exported_w;
-  int exported_back_y, exported_front_y, exported_h;
-  struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS];
-  unsigned int status[4];
-  unsigned int last_wrap;
-  drm_mga_age_t last_frame;
-  unsigned int last_enqueue;
-  unsigned int last_dispatch;
-  unsigned int last_quiescent;
-  struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1];
-  unsigned int texAge[MGA_NR_TEX_HEAPS];
-  int ctxOwner;
-} drm_mga_sarea_t;
-#define DRM_MGA_INIT 0x00
-#define DRM_MGA_FLUSH 0x01
-#define DRM_MGA_RESET 0x02
-#define DRM_MGA_SWAP 0x03
-#define DRM_MGA_CLEAR 0x04
-#define DRM_MGA_VERTEX 0x05
-#define DRM_MGA_INDICES 0x06
-#define DRM_MGA_ILOAD 0x07
-#define DRM_MGA_BLIT 0x08
-#define DRM_MGA_GETPARAM 0x09
-#define DRM_MGA_SET_FENCE 0x0a
-#define DRM_MGA_WAIT_FENCE 0x0b
-#define DRM_MGA_DMA_BOOTSTRAP 0x0c
-#define DRM_IOCTL_MGA_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t)
-#define DRM_IOCTL_MGA_FLUSH DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_FLUSH, struct drm_lock)
-#define DRM_IOCTL_MGA_RESET DRM_IO(DRM_COMMAND_BASE + DRM_MGA_RESET)
-#define DRM_IOCTL_MGA_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_MGA_SWAP)
-#define DRM_IOCTL_MGA_CLEAR DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t)
-#define DRM_IOCTL_MGA_VERTEX DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t)
-#define DRM_IOCTL_MGA_INDICES DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t)
-#define DRM_IOCTL_MGA_ILOAD DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
-#define DRM_IOCTL_MGA_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
-#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
-#define DRM_IOCTL_MGA_SET_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, __u32)
-#define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, __u32)
-#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t)
-typedef struct _drm_mga_warp_index {
-  int installed;
-  unsigned long phys_addr;
-  int size;
-} drm_mga_warp_index_t;
-typedef struct drm_mga_init {
-  enum {
-    MGA_INIT_DMA = 0x01,
-    MGA_CLEANUP_DMA = 0x02
-  } func;
-  unsigned long sarea_priv_offset;
-  __struct_group(, always32bit,, int chipset;
-  int sgram;
-  unsigned int maccess;
-  unsigned int fb_cpp;
-  unsigned int front_offset, front_pitch;
-  unsigned int back_offset, back_pitch;
-  unsigned int depth_cpp;
-  unsigned int depth_offset, depth_pitch;
-  unsigned int texture_offset[MGA_NR_TEX_HEAPS];
-  unsigned int texture_size[MGA_NR_TEX_HEAPS];
- );
-  unsigned long fb_offset;
-  unsigned long mmio_offset;
-  unsigned long status_offset;
-  unsigned long warp_offset;
-  unsigned long primary_offset;
-  unsigned long buffers_offset;
-} drm_mga_init_t;
-typedef struct drm_mga_dma_bootstrap {
-  unsigned long texture_handle;
-  __u32 texture_size;
-  __u32 primary_size;
-  __u32 secondary_bin_count;
-  __u32 secondary_bin_size;
-  __u32 agp_mode;
-  __u8 agp_size;
-} drm_mga_dma_bootstrap_t;
-typedef struct drm_mga_clear {
-  unsigned int flags;
-  unsigned int clear_color;
-  unsigned int clear_depth;
-  unsigned int color_mask;
-  unsigned int depth_mask;
-} drm_mga_clear_t;
-typedef struct drm_mga_vertex {
-  int idx;
-  int used;
-  int discard;
-} drm_mga_vertex_t;
-typedef struct drm_mga_indices {
-  int idx;
-  unsigned int start;
-  unsigned int end;
-  int discard;
-} drm_mga_indices_t;
-typedef struct drm_mga_iload {
-  int idx;
-  unsigned int dstorg;
-  unsigned int length;
-} drm_mga_iload_t;
-typedef struct _drm_mga_blit {
-  unsigned int planemask;
-  unsigned int srcorg;
-  unsigned int dstorg;
-  int src_pitch, dst_pitch;
-  int delta_sx, delta_sy;
-  int delta_dx, delta_dy;
-  int height, ydir;
-  int source_pitch, dest_pitch;
-} drm_mga_blit_t;
-#define MGA_PARAM_IRQ_NR 1
-#define MGA_PARAM_CARD_TYPE 2
-typedef struct drm_mga_getparam {
-  int param;
-  void  * value;
-} drm_mga_getparam_t;
-#ifdef __cplusplus
-}
-#endif
-#endif
diff --git a/libc/kernel/uapi/drm/msm_drm.h b/libc/kernel/uapi/drm/msm_drm.h
index ad3a971..f5a4627 100644
--- a/libc/kernel/uapi/drm/msm_drm.h
+++ b/libc/kernel/uapi/drm/msm_drm.h
@@ -116,7 +116,8 @@
 #define MSM_SUBMIT_BO_READ 0x0001
 #define MSM_SUBMIT_BO_WRITE 0x0002
 #define MSM_SUBMIT_BO_DUMP 0x0004
-#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE | MSM_SUBMIT_BO_DUMP)
+#define MSM_SUBMIT_BO_NO_IMPLICIT 0x0008
+#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE | MSM_SUBMIT_BO_DUMP | MSM_SUBMIT_BO_NO_IMPLICIT)
 struct drm_msm_gem_submit_bo {
   __u32 flags;
   __u32 handle;
diff --git a/libc/kernel/uapi/drm/r128_drm.h b/libc/kernel/uapi/drm/r128_drm.h
deleted file mode 100644
index 3e013b1..0000000
--- a/libc/kernel/uapi/drm/r128_drm.h
+++ /dev/null
@@ -1,235 +0,0 @@
-/****************************************************************************
- ****************************************************************************
- ***
- ***   This header was automatically generated from a Linux kernel header
- ***   of the same name, to make information necessary for userspace to
- ***   call into the kernel available to libc.  It contains only constants,
- ***   structures, and macros generated from the original header, and thus,
- ***   contains no copyrightable information.
- ***
- ***   To edit the content of this header, modify the corresponding
- ***   source file (e.g. under external/kernel-headers/original/) then
- ***   run bionic/libc/kernel/tools/update_all.py
- ***
- ***   Any manual change here will be lost the next time this script will
- ***   be run. You've been warned!
- ***
- ****************************************************************************
- ****************************************************************************/
-#ifndef __R128_DRM_H__
-#define __R128_DRM_H__
-#include "drm.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-#ifndef __R128_SAREA_DEFINES__
-#define __R128_SAREA_DEFINES__
-#define R128_UPLOAD_CONTEXT 0x001
-#define R128_UPLOAD_SETUP 0x002
-#define R128_UPLOAD_TEX0 0x004
-#define R128_UPLOAD_TEX1 0x008
-#define R128_UPLOAD_TEX0IMAGES 0x010
-#define R128_UPLOAD_TEX1IMAGES 0x020
-#define R128_UPLOAD_CORE 0x040
-#define R128_UPLOAD_MASKS 0x080
-#define R128_UPLOAD_WINDOW 0x100
-#define R128_UPLOAD_CLIPRECTS 0x200
-#define R128_REQUIRE_QUIESCENCE 0x400
-#define R128_UPLOAD_ALL 0x7ff
-#define R128_FRONT 0x1
-#define R128_BACK 0x2
-#define R128_DEPTH 0x4
-#define R128_POINTS 0x1
-#define R128_LINES 0x2
-#define R128_LINE_STRIP 0x3
-#define R128_TRIANGLES 0x4
-#define R128_TRIANGLE_FAN 0x5
-#define R128_TRIANGLE_STRIP 0x6
-#define R128_BUFFER_SIZE 16384
-#define R128_INDEX_PRIM_OFFSET 20
-#define R128_HOSTDATA_BLIT_OFFSET 32
-#define R128_NR_SAREA_CLIPRECTS 12
-#define R128_LOCAL_TEX_HEAP 0
-#define R128_AGP_TEX_HEAP 1
-#define R128_NR_TEX_HEAPS 2
-#define R128_NR_TEX_REGIONS 64
-#define R128_LOG_TEX_GRANULARITY 16
-#define R128_NR_CONTEXT_REGS 12
-#define R128_MAX_TEXTURE_LEVELS 11
-#define R128_MAX_TEXTURE_UNITS 2
-#endif
-typedef struct {
-  unsigned int dst_pitch_offset_c;
-  unsigned int dp_gui_master_cntl_c;
-  unsigned int sc_top_left_c;
-  unsigned int sc_bottom_right_c;
-  unsigned int z_offset_c;
-  unsigned int z_pitch_c;
-  unsigned int z_sten_cntl_c;
-  unsigned int tex_cntl_c;
-  unsigned int misc_3d_state_cntl_reg;
-  unsigned int texture_clr_cmp_clr_c;
-  unsigned int texture_clr_cmp_msk_c;
-  unsigned int fog_color_c;
-  unsigned int tex_size_pitch_c;
-  unsigned int constant_color_c;
-  unsigned int pm4_vc_fpu_setup;
-  unsigned int setup_cntl;
-  unsigned int dp_write_mask;
-  unsigned int sten_ref_mask_c;
-  unsigned int plane_3d_mask_c;
-  unsigned int window_xy_offset;
-  unsigned int scale_3d_cntl;
-} drm_r128_context_regs_t;
-typedef struct {
-  unsigned int tex_cntl;
-  unsigned int tex_combine_cntl;
-  unsigned int tex_size_pitch;
-  unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS];
-  unsigned int tex_border_color;
-} drm_r128_texture_regs_t;
-typedef struct drm_r128_sarea {
-  drm_r128_context_regs_t context_state;
-  drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS];
-  unsigned int dirty;
-  unsigned int vertsize;
-  unsigned int vc_format;
-  struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS];
-  unsigned int nbox;
-  unsigned int last_frame;
-  unsigned int last_dispatch;
-  struct drm_tex_region tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1];
-  unsigned int tex_age[R128_NR_TEX_HEAPS];
-  int ctx_owner;
-  int pfAllowPageFlip;
-  int pfCurrentPage;
-} drm_r128_sarea_t;
-#define DRM_R128_INIT 0x00
-#define DRM_R128_CCE_START 0x01
-#define DRM_R128_CCE_STOP 0x02
-#define DRM_R128_CCE_RESET 0x03
-#define DRM_R128_CCE_IDLE 0x04
-#define DRM_R128_RESET 0x06
-#define DRM_R128_SWAP 0x07
-#define DRM_R128_CLEAR 0x08
-#define DRM_R128_VERTEX 0x09
-#define DRM_R128_INDICES 0x0a
-#define DRM_R128_BLIT 0x0b
-#define DRM_R128_DEPTH 0x0c
-#define DRM_R128_STIPPLE 0x0d
-#define DRM_R128_INDIRECT 0x0f
-#define DRM_R128_FULLSCREEN 0x10
-#define DRM_R128_CLEAR2 0x11
-#define DRM_R128_GETPARAM 0x12
-#define DRM_R128_FLIP 0x13
-#define DRM_IOCTL_R128_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t)
-#define DRM_IOCTL_R128_CCE_START DRM_IO(DRM_COMMAND_BASE + DRM_R128_CCE_START)
-#define DRM_IOCTL_R128_CCE_STOP DRM_IOW(DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t)
-#define DRM_IOCTL_R128_CCE_RESET DRM_IO(DRM_COMMAND_BASE + DRM_R128_CCE_RESET)
-#define DRM_IOCTL_R128_CCE_IDLE DRM_IO(DRM_COMMAND_BASE + DRM_R128_CCE_IDLE)
-#define DRM_IOCTL_R128_RESET DRM_IO(DRM_COMMAND_BASE + DRM_R128_RESET)
-#define DRM_IOCTL_R128_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_R128_SWAP)
-#define DRM_IOCTL_R128_CLEAR DRM_IOW(DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t)
-#define DRM_IOCTL_R128_VERTEX DRM_IOW(DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t)
-#define DRM_IOCTL_R128_INDICES DRM_IOW(DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t)
-#define DRM_IOCTL_R128_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t)
-#define DRM_IOCTL_R128_DEPTH DRM_IOW(DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t)
-#define DRM_IOCTL_R128_STIPPLE DRM_IOW(DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t)
-#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t)
-#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW(DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t)
-#define DRM_IOCTL_R128_CLEAR2 DRM_IOW(DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t)
-#define DRM_IOCTL_R128_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t)
-#define DRM_IOCTL_R128_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_R128_FLIP)
-typedef struct drm_r128_init {
-  enum {
-    R128_INIT_CCE = 0x01,
-    R128_CLEANUP_CCE = 0x02
-  } func;
-  unsigned long sarea_priv_offset;
-  int is_pci;
-  int cce_mode;
-  int cce_secure;
-  int ring_size;
-  int usec_timeout;
-  unsigned int fb_bpp;
-  unsigned int front_offset, front_pitch;
-  unsigned int back_offset, back_pitch;
-  unsigned int depth_bpp;
-  unsigned int depth_offset, depth_pitch;
-  unsigned int span_offset;
-  unsigned long fb_offset;
-  unsigned long mmio_offset;
-  unsigned long ring_offset;
-  unsigned long ring_rptr_offset;
-  unsigned long buffers_offset;
-  unsigned long agp_textures_offset;
-} drm_r128_init_t;
-typedef struct drm_r128_cce_stop {
-  int flush;
-  int idle;
-} drm_r128_cce_stop_t;
-typedef struct drm_r128_clear {
-  unsigned int flags;
-  unsigned int clear_color;
-  unsigned int clear_depth;
-  unsigned int color_mask;
-  unsigned int depth_mask;
-} drm_r128_clear_t;
-typedef struct drm_r128_vertex {
-  int prim;
-  int idx;
-  int count;
-  int discard;
-} drm_r128_vertex_t;
-typedef struct drm_r128_indices {
-  int prim;
-  int idx;
-  int start;
-  int end;
-  int discard;
-} drm_r128_indices_t;
-typedef struct drm_r128_blit {
-  int idx;
-  int pitch;
-  int offset;
-  int format;
-  unsigned short x, y;
-  unsigned short width, height;
-} drm_r128_blit_t;
-typedef struct drm_r128_depth {
-  enum {
-    R128_WRITE_SPAN = 0x01,
-    R128_WRITE_PIXELS = 0x02,
-    R128_READ_SPAN = 0x03,
-    R128_READ_PIXELS = 0x04
-  } func;
-  int n;
-  int  * x;
-  int  * y;
-  unsigned int  * buffer;
-  unsigned char  * mask;
-} drm_r128_depth_t;
-typedef struct drm_r128_stipple {
-  unsigned int  * mask;
-} drm_r128_stipple_t;
-typedef struct drm_r128_indirect {
-  int idx;
-  int start;
-  int end;
-  int discard;
-} drm_r128_indirect_t;
-typedef struct drm_r128_fullscreen {
-  enum {
-    R128_INIT_FULLSCREEN = 0x01,
-    R128_CLEANUP_FULLSCREEN = 0x02
-  } func;
-} drm_r128_fullscreen_t;
-#define R128_PARAM_IRQ_NR 1
-typedef struct drm_r128_getparam {
-  int param;
-  void  * value;
-} drm_r128_getparam_t;
-#ifdef __cplusplus
-}
-#endif
-#endif
diff --git a/libc/kernel/uapi/drm/savage_drm.h b/libc/kernel/uapi/drm/savage_drm.h
deleted file mode 100644
index efc0ae6..0000000
--- a/libc/kernel/uapi/drm/savage_drm.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/****************************************************************************
- ****************************************************************************
- ***
- ***   This header was automatically generated from a Linux kernel header
- ***   of the same name, to make information necessary for userspace to
- ***   call into the kernel available to libc.  It contains only constants,
- ***   structures, and macros generated from the original header, and thus,
- ***   contains no copyrightable information.
- ***
- ***   To edit the content of this header, modify the corresponding
- ***   source file (e.g. under external/kernel-headers/original/) then
- ***   run bionic/libc/kernel/tools/update_all.py
- ***
- ***   Any manual change here will be lost the next time this script will
- ***   be run. You've been warned!
- ***
- ****************************************************************************
- ****************************************************************************/
-#ifndef __SAVAGE_DRM_H__
-#define __SAVAGE_DRM_H__
-#include "drm.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-#ifndef __SAVAGE_SAREA_DEFINES__
-#define __SAVAGE_SAREA_DEFINES__
-#define SAVAGE_CARD_HEAP 0
-#define SAVAGE_AGP_HEAP 1
-#define SAVAGE_NR_TEX_HEAPS 2
-#define SAVAGE_NR_TEX_REGIONS 16
-#define SAVAGE_LOG_MIN_TEX_REGION_SIZE 16
-#endif
-typedef struct _drm_savage_sarea {
-  struct drm_tex_region texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS + 1];
-  unsigned int texAge[SAVAGE_NR_TEX_HEAPS];
-  int ctxOwner;
-} drm_savage_sarea_t, * drm_savage_sarea_ptr;
-#define DRM_SAVAGE_BCI_INIT 0x00
-#define DRM_SAVAGE_BCI_CMDBUF 0x01
-#define DRM_SAVAGE_BCI_EVENT_EMIT 0x02
-#define DRM_SAVAGE_BCI_EVENT_WAIT 0x03
-#define DRM_IOCTL_SAVAGE_BCI_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_INIT, drm_savage_init_t)
-#define DRM_IOCTL_SAVAGE_BCI_CMDBUF DRM_IOW(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_CMDBUF, drm_savage_cmdbuf_t)
-#define DRM_IOCTL_SAVAGE_BCI_EVENT_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_EMIT, drm_savage_event_emit_t)
-#define DRM_IOCTL_SAVAGE_BCI_EVENT_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_WAIT, drm_savage_event_wait_t)
-#define SAVAGE_DMA_PCI 1
-#define SAVAGE_DMA_AGP 3
-typedef struct drm_savage_init {
-  enum {
-    SAVAGE_INIT_BCI = 1,
-    SAVAGE_CLEANUP_BCI = 2
-  } func;
-  unsigned int sarea_priv_offset;
-  unsigned int cob_size;
-  unsigned int bci_threshold_lo, bci_threshold_hi;
-  unsigned int dma_type;
-  unsigned int fb_bpp;
-  unsigned int front_offset, front_pitch;
-  unsigned int back_offset, back_pitch;
-  unsigned int depth_bpp;
-  unsigned int depth_offset, depth_pitch;
-  unsigned int texture_offset;
-  unsigned int texture_size;
-  unsigned long status_offset;
-  unsigned long buffers_offset;
-  unsigned long agp_textures_offset;
-  unsigned long cmd_dma_offset;
-} drm_savage_init_t;
-typedef union drm_savage_cmd_header drm_savage_cmd_header_t;
-typedef struct drm_savage_cmdbuf {
-  drm_savage_cmd_header_t  * cmd_addr;
-  unsigned int size;
-  unsigned int dma_idx;
-  int discard;
-  unsigned int  * vb_addr;
-  unsigned int vb_size;
-  unsigned int vb_stride;
-  struct drm_clip_rect  * box_addr;
-  unsigned int nbox;
-} drm_savage_cmdbuf_t;
-#define SAVAGE_WAIT_2D 0x1
-#define SAVAGE_WAIT_3D 0x2
-#define SAVAGE_WAIT_IRQ 0x4
-typedef struct drm_savage_event {
-  unsigned int count;
-  unsigned int flags;
-} drm_savage_event_emit_t, drm_savage_event_wait_t;
-#define SAVAGE_CMD_STATE 0
-#define SAVAGE_CMD_DMA_PRIM 1
-#define SAVAGE_CMD_VB_PRIM 2
-#define SAVAGE_CMD_DMA_IDX 3
-#define SAVAGE_CMD_VB_IDX 4
-#define SAVAGE_CMD_CLEAR 5
-#define SAVAGE_CMD_SWAP 6
-#define SAVAGE_PRIM_TRILIST 0
-#define SAVAGE_PRIM_TRISTRIP 1
-#define SAVAGE_PRIM_TRIFAN 2
-#define SAVAGE_PRIM_TRILIST_201 3
-#define SAVAGE_SKIP_Z 0x01
-#define SAVAGE_SKIP_W 0x02
-#define SAVAGE_SKIP_C0 0x04
-#define SAVAGE_SKIP_C1 0x08
-#define SAVAGE_SKIP_S0 0x10
-#define SAVAGE_SKIP_T0 0x20
-#define SAVAGE_SKIP_ST0 0x30
-#define SAVAGE_SKIP_S1 0x40
-#define SAVAGE_SKIP_T1 0x80
-#define SAVAGE_SKIP_ST1 0xc0
-#define SAVAGE_SKIP_ALL_S3D 0x3f
-#define SAVAGE_SKIP_ALL_S4 0xff
-#define SAVAGE_FRONT 0x1
-#define SAVAGE_BACK 0x2
-#define SAVAGE_DEPTH 0x4
-union drm_savage_cmd_header {
-  struct {
-    unsigned char cmd;
-    unsigned char pad0;
-    unsigned short pad1;
-    unsigned short pad2;
-    unsigned short pad3;
-  } cmd;
-  struct {
-    unsigned char cmd;
-    unsigned char global;
-    unsigned short count;
-    unsigned short start;
-    unsigned short pad3;
-  } state;
-  struct {
-    unsigned char cmd;
-    unsigned char prim;
-    unsigned short skip;
-    unsigned short count;
-    unsigned short start;
-  } prim;
-  struct {
-    unsigned char cmd;
-    unsigned char prim;
-    unsigned short skip;
-    unsigned short count;
-    unsigned short pad3;
-  } idx;
-  struct {
-    unsigned char cmd;
-    unsigned char pad0;
-    unsigned short pad1;
-    unsigned int flags;
-  } clear0;
-  struct {
-    unsigned int mask;
-    unsigned int value;
-  } clear1;
-};
-#ifdef __cplusplus
-}
-#endif
-#endif
diff --git a/libc/kernel/uapi/drm/sis_drm.h b/libc/kernel/uapi/drm/sis_drm.h
deleted file mode 100644
index 1606a85..0000000
--- a/libc/kernel/uapi/drm/sis_drm.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/****************************************************************************
- ****************************************************************************
- ***
- ***   This header was automatically generated from a Linux kernel header
- ***   of the same name, to make information necessary for userspace to
- ***   call into the kernel available to libc.  It contains only constants,
- ***   structures, and macros generated from the original header, and thus,
- ***   contains no copyrightable information.
- ***
- ***   To edit the content of this header, modify the corresponding
- ***   source file (e.g. under external/kernel-headers/original/) then
- ***   run bionic/libc/kernel/tools/update_all.py
- ***
- ***   Any manual change here will be lost the next time this script will
- ***   be run. You've been warned!
- ***
- ****************************************************************************
- ****************************************************************************/
-#ifndef __SIS_DRM_H__
-#define __SIS_DRM_H__
-#include "drm.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-#define NOT_USED_0_3
-#define DRM_SIS_FB_ALLOC 0x04
-#define DRM_SIS_FB_FREE 0x05
-#define NOT_USED_6_12
-#define DRM_SIS_AGP_INIT 0x13
-#define DRM_SIS_AGP_ALLOC 0x14
-#define DRM_SIS_AGP_FREE 0x15
-#define DRM_SIS_FB_INIT 0x16
-#define DRM_IOCTL_SIS_FB_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_FB_ALLOC, drm_sis_mem_t)
-#define DRM_IOCTL_SIS_FB_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_SIS_FB_FREE, drm_sis_mem_t)
-#define DRM_IOCTL_SIS_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_AGP_INIT, drm_sis_agp_t)
-#define DRM_IOCTL_SIS_AGP_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_AGP_ALLOC, drm_sis_mem_t)
-#define DRM_IOCTL_SIS_AGP_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_SIS_AGP_FREE, drm_sis_mem_t)
-#define DRM_IOCTL_SIS_FB_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_SIS_FB_INIT, drm_sis_fb_t)
-typedef struct {
-  int context;
-  unsigned long offset;
-  unsigned long size;
-  unsigned long free;
-} drm_sis_mem_t;
-typedef struct {
-  unsigned long offset, size;
-} drm_sis_agp_t;
-typedef struct {
-  unsigned long offset, size;
-} drm_sis_fb_t;
-#ifdef __cplusplus
-}
-#endif
-#endif
diff --git a/libc/kernel/uapi/drm/via_drm.h b/libc/kernel/uapi/drm/via_drm.h
deleted file mode 100644
index 95a149b..0000000
--- a/libc/kernel/uapi/drm/via_drm.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/****************************************************************************
- ****************************************************************************
- ***
- ***   This header was automatically generated from a Linux kernel header
- ***   of the same name, to make information necessary for userspace to
- ***   call into the kernel available to libc.  It contains only constants,
- ***   structures, and macros generated from the original header, and thus,
- ***   contains no copyrightable information.
- ***
- ***   To edit the content of this header, modify the corresponding
- ***   source file (e.g. under external/kernel-headers/original/) then
- ***   run bionic/libc/kernel/tools/update_all.py
- ***
- ***   Any manual change here will be lost the next time this script will
- ***   be run. You've been warned!
- ***
- ****************************************************************************
- ****************************************************************************/
-#ifndef _VIA_DRM_H_
-#define _VIA_DRM_H_
-#include "drm.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-#ifndef _VIA_DEFINES_
-#define _VIA_DEFINES_
-#define VIA_NR_SAREA_CLIPRECTS 8
-#define VIA_NR_XVMC_PORTS 10
-#define VIA_NR_XVMC_LOCKS 5
-#define VIA_MAX_CACHELINE_SIZE 64
-#define XVMCLOCKPTR(saPriv,lockNo) ((volatile struct drm_hw_lock *) (((((unsigned long) (saPriv)->XvMCLockArea) + (VIA_MAX_CACHELINE_SIZE - 1)) & ~(VIA_MAX_CACHELINE_SIZE - 1)) + VIA_MAX_CACHELINE_SIZE * (lockNo)))
-#define VIA_NR_TEX_REGIONS 64
-#define VIA_LOG_MIN_TEX_REGION_SIZE 16
-#endif
-#define VIA_UPLOAD_TEX0IMAGE 0x1
-#define VIA_UPLOAD_TEX1IMAGE 0x2
-#define VIA_UPLOAD_CTX 0x4
-#define VIA_UPLOAD_BUFFERS 0x8
-#define VIA_UPLOAD_TEX0 0x10
-#define VIA_UPLOAD_TEX1 0x20
-#define VIA_UPLOAD_CLIPRECTS 0x40
-#define VIA_UPLOAD_ALL 0xff
-#define DRM_VIA_ALLOCMEM 0x00
-#define DRM_VIA_FREEMEM 0x01
-#define DRM_VIA_AGP_INIT 0x02
-#define DRM_VIA_FB_INIT 0x03
-#define DRM_VIA_MAP_INIT 0x04
-#define DRM_VIA_DEC_FUTEX 0x05
-#define NOT_USED
-#define DRM_VIA_DMA_INIT 0x07
-#define DRM_VIA_CMDBUFFER 0x08
-#define DRM_VIA_FLUSH 0x09
-#define DRM_VIA_PCICMD 0x0a
-#define DRM_VIA_CMDBUF_SIZE 0x0b
-#define NOT_USED
-#define DRM_VIA_WAIT_IRQ 0x0d
-#define DRM_VIA_DMA_BLIT 0x0e
-#define DRM_VIA_BLIT_SYNC 0x0f
-#define DRM_IOCTL_VIA_ALLOCMEM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t)
-#define DRM_IOCTL_VIA_FREEMEM DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t)
-#define DRM_IOCTL_VIA_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t)
-#define DRM_IOCTL_VIA_FB_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t)
-#define DRM_IOCTL_VIA_MAP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t)
-#define DRM_IOCTL_VIA_DEC_FUTEX DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t)
-#define DRM_IOCTL_VIA_DMA_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t)
-#define DRM_IOCTL_VIA_CMDBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t)
-#define DRM_IOCTL_VIA_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_VIA_FLUSH)
-#define DRM_IOCTL_VIA_PCICMD DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t)
-#define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, drm_via_cmdbuf_size_t)
-#define DRM_IOCTL_VIA_WAIT_IRQ DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t)
-#define DRM_IOCTL_VIA_DMA_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DMA_BLIT, drm_via_dmablit_t)
-#define DRM_IOCTL_VIA_BLIT_SYNC DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_BLIT_SYNC, drm_via_blitsync_t)
-#define VIA_TEX_SETUP_SIZE 8
-#define VIA_FRONT 0x1
-#define VIA_BACK 0x2
-#define VIA_DEPTH 0x4
-#define VIA_STENCIL 0x8
-#define VIA_MEM_VIDEO 0
-#define VIA_MEM_AGP 1
-#define VIA_MEM_SYSTEM 2
-#define VIA_MEM_MIXED 3
-#define VIA_MEM_UNKNOWN 4
-typedef struct {
-  __u32 offset;
-  __u32 size;
-} drm_via_agp_t;
-typedef struct {
-  __u32 offset;
-  __u32 size;
-} drm_via_fb_t;
-typedef struct {
-  __u32 context;
-  __u32 type;
-  __u32 size;
-  unsigned long index;
-  unsigned long offset;
-} drm_via_mem_t;
-typedef struct _drm_via_init {
-  enum {
-    VIA_INIT_MAP = 0x01,
-    VIA_CLEANUP_MAP = 0x02
-  } func;
-  unsigned long sarea_priv_offset;
-  unsigned long fb_offset;
-  unsigned long mmio_offset;
-  unsigned long agpAddr;
-} drm_via_init_t;
-typedef struct _drm_via_futex {
-  enum {
-    VIA_FUTEX_WAIT = 0x00,
-    VIA_FUTEX_WAKE = 0X01
-  } func;
-  __u32 ms;
-  __u32 lock;
-  __u32 val;
-} drm_via_futex_t;
-typedef struct _drm_via_dma_init {
-  enum {
-    VIA_INIT_DMA = 0x01,
-    VIA_CLEANUP_DMA = 0x02,
-    VIA_DMA_INITIALIZED = 0x03
-  } func;
-  unsigned long offset;
-  unsigned long size;
-  unsigned long reg_pause_addr;
-} drm_via_dma_init_t;
-typedef struct _drm_via_cmdbuffer {
-  char  * buf;
-  unsigned long size;
-} drm_via_cmdbuffer_t;
-typedef struct _drm_via_tex_region {
-  unsigned char next, prev;
-  unsigned char inUse;
-  int age;
-} drm_via_tex_region_t;
-typedef struct _drm_via_sarea {
-  unsigned int dirty;
-  unsigned int nbox;
-  struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS];
-  drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1];
-  int texAge;
-  int ctxOwner;
-  int vertexPrim;
-  char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)];
-  unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS];
-  unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS];
-  unsigned int XvMCCtxNoGrabbed;
-  unsigned int pfCurrentOffset;
-} drm_via_sarea_t;
-typedef struct _drm_via_cmdbuf_size {
-  enum {
-    VIA_CMDBUF_SPACE = 0x01,
-    VIA_CMDBUF_LAG = 0x02
-  } func;
-  int wait;
-  __u32 size;
-} drm_via_cmdbuf_size_t;
-typedef enum {
-  VIA_IRQ_ABSOLUTE = 0x0,
-  VIA_IRQ_RELATIVE = 0x1,
-  VIA_IRQ_SIGNAL = 0x10000000,
-  VIA_IRQ_FORCE_SEQUENCE = 0x20000000
-} via_irq_seq_type_t;
-#define VIA_IRQ_FLAGS_MASK 0xF0000000
-enum drm_via_irqs {
-  drm_via_irq_hqv0 = 0,
-  drm_via_irq_hqv1,
-  drm_via_irq_dma0_dd,
-  drm_via_irq_dma0_td,
-  drm_via_irq_dma1_dd,
-  drm_via_irq_dma1_td,
-  drm_via_irq_num
-};
-struct drm_via_wait_irq_request {
-  unsigned irq;
-  via_irq_seq_type_t type;
-  __u32 sequence;
-  __u32 signal;
-};
-typedef union drm_via_irqwait {
-  struct drm_via_wait_irq_request request;
-  struct drm_wait_vblank_reply reply;
-} drm_via_irqwait_t;
-typedef struct drm_via_blitsync {
-  __u32 sync_handle;
-  unsigned engine;
-} drm_via_blitsync_t;
-typedef struct drm_via_dmablit {
-  __u32 num_lines;
-  __u32 line_length;
-  __u32 fb_addr;
-  __u32 fb_stride;
-  unsigned char * mem_addr;
-  __u32 mem_stride;
-  __u32 flags;
-  int to_fb;
-  drm_via_blitsync_t sync;
-} drm_via_dmablit_t;
-#ifdef __cplusplus
-}
-#endif
-#endif