Update to kernel headers v5.2.
Test: Booted a taimen, ran unit bionic unit tests.
Change-Id: I3522c59793bbcef98ea515996a481d92f14b8816
diff --git a/libc/kernel/uapi/linux/pci_regs.h b/libc/kernel/uapi/linux/pci_regs.h
index d75d200..4c8cc95 100644
--- a/libc/kernel/uapi/linux/pci_regs.h
+++ b/libc/kernel/uapi/linux/pci_regs.h
@@ -275,7 +275,7 @@
#define PCI_MSIX_ENTRY_UPPER_ADDR 4
#define PCI_MSIX_ENTRY_DATA 8
#define PCI_MSIX_ENTRY_VECTOR_CTRL 12
-#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1
+#define PCI_MSIX_ENTRY_CTRL_MASKBIT 0x00000001
#define PCI_CHSWP_CSR 2
#define PCI_CHSWP_DHA 0x01
#define PCI_CHSWP_EIM 0x02
@@ -299,6 +299,9 @@
#define PCI_EA_FIRST_ENT_BRIDGE 8
#define PCI_EA_ES 0x00000007
#define PCI_EA_BEI 0x000000f0
+#define PCI_EA_SEC_BUS_MASK 0xff
+#define PCI_EA_SUB_BUS_MASK 0xff00
+#define PCI_EA_SUB_BUS_SHIFT 8
#define PCI_EA_BEI_BAR0 0
#define PCI_EA_BEI_BAR5 5
#define PCI_EA_BEI_BRIDGE 6
@@ -746,12 +749,12 @@
#define PCI_ATS_MIN_STU 12
#define PCI_EXT_CAP_ATS_SIZEOF 8
#define PCI_PRI_CTRL 0x04
-#define PCI_PRI_CTRL_ENABLE 0x01
-#define PCI_PRI_CTRL_RESET 0x02
+#define PCI_PRI_CTRL_ENABLE 0x0001
+#define PCI_PRI_CTRL_RESET 0x0002
#define PCI_PRI_STATUS 0x06
-#define PCI_PRI_STATUS_RF 0x001
-#define PCI_PRI_STATUS_UPRGI 0x002
-#define PCI_PRI_STATUS_STOPPED 0x100
+#define PCI_PRI_STATUS_RF 0x0001
+#define PCI_PRI_STATUS_UPRGI 0x0002
+#define PCI_PRI_STATUS_STOPPED 0x0100
#define PCI_PRI_STATUS_PASID 0x8000
#define PCI_PRI_MAX_REQ 0x08
#define PCI_PRI_ALLOC_REQ 0x0c
@@ -765,16 +768,16 @@
#define PCI_PASID_CTRL_PRIV 0x04
#define PCI_EXT_CAP_PASID_SIZEOF 8
#define PCI_SRIOV_CAP 0x04
-#define PCI_SRIOV_CAP_VFM 0x01
+#define PCI_SRIOV_CAP_VFM 0x00000001
#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21)
#define PCI_SRIOV_CTRL 0x08
-#define PCI_SRIOV_CTRL_VFE 0x01
-#define PCI_SRIOV_CTRL_VFM 0x02
-#define PCI_SRIOV_CTRL_INTR 0x04
-#define PCI_SRIOV_CTRL_MSE 0x08
-#define PCI_SRIOV_CTRL_ARI 0x10
+#define PCI_SRIOV_CTRL_VFE 0x0001
+#define PCI_SRIOV_CTRL_VFM 0x0002
+#define PCI_SRIOV_CTRL_INTR 0x0004
+#define PCI_SRIOV_CTRL_MSE 0x0008
+#define PCI_SRIOV_CTRL_ARI 0x0010
#define PCI_SRIOV_STATUS 0x0a
-#define PCI_SRIOV_STATUS_VFM 0x01
+#define PCI_SRIOV_STATUS_VFM 0x0001
#define PCI_SRIOV_INITIAL_VF 0x0c
#define PCI_SRIOV_TOTAL_VF 0x0e
#define PCI_SRIOV_NUM_VF 0x10
@@ -801,13 +804,13 @@
#define PCI_LTR_SCALE_SHIFT 10
#define PCI_EXT_CAP_LTR_SIZEOF 8
#define PCI_ACS_CAP 0x04
-#define PCI_ACS_SV 0x01
-#define PCI_ACS_TB 0x02
-#define PCI_ACS_RR 0x04
-#define PCI_ACS_CR 0x08
-#define PCI_ACS_UF 0x10
-#define PCI_ACS_EC 0x20
-#define PCI_ACS_DT 0x40
+#define PCI_ACS_SV 0x0001
+#define PCI_ACS_TB 0x0002
+#define PCI_ACS_RR 0x0004
+#define PCI_ACS_CR 0x0008
+#define PCI_ACS_UF 0x0010
+#define PCI_ACS_EC 0x0020
+#define PCI_ACS_DT 0x0040
#define PCI_ACS_EGRESS_BITS 0x05
#define PCI_ACS_CTRL 0x06
#define PCI_ACS_EGRESS_CTL_V 0x08