Update to kernel headers v5.2.
Test: Booted a taimen, ran unit bionic unit tests.
Change-Id: I3522c59793bbcef98ea515996a481d92f14b8816
diff --git a/libc/kernel/uapi/drm/amdgpu_drm.h b/libc/kernel/uapi/drm/amdgpu_drm.h
index 53da9dd..193881d 100644
--- a/libc/kernel/uapi/drm/amdgpu_drm.h
+++ b/libc/kernel/uapi/drm/amdgpu_drm.h
@@ -117,6 +117,8 @@
#define AMDGPU_CTX_QUERY2_FLAGS_RESET (1 << 0)
#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1 << 1)
#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1 << 2)
+#define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1 << 3)
+#define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1 << 4)
#define AMDGPU_CTX_PRIORITY_UNSET - 2048
#define AMDGPU_CTX_PRIORITY_VERY_LOW - 1023
#define AMDGPU_CTX_PRIORITY_LOW - 512
@@ -325,6 +327,8 @@
#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
#define AMDGPU_CHUNK_ID_BO_HANDLES 0x06
#define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07
+#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08
+#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09
struct drm_amdgpu_cs_chunk {
__u32 chunk_id;
__u32 length_dw;
@@ -372,6 +376,11 @@
struct drm_amdgpu_cs_chunk_sem {
__u32 handle;
};
+struct drm_amdgpu_cs_chunk_syncobj {
+ __u32 handle;
+ __u32 flags;
+ __u64 point;
+};
#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0
#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1
#define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2
@@ -416,6 +425,7 @@
#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
#define AMDGPU_INFO_FW_DMCU 0x12
+#define AMDGPU_INFO_FW_TA 0x13
#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
#define AMDGPU_INFO_VRAM_USAGE 0x10
#define AMDGPU_INFO_GTT_USAGE 0x11
@@ -443,6 +453,21 @@
#define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9
#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
+#define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20
+#define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0)
+#define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1)
+#define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2)
+#define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3)
+#define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4)
+#define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5)
+#define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6)
+#define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7)
+#define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8)
+#define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9)
+#define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10)
+#define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11)
+#define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12)
+#define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13)
#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8