diff --git a/libc/kernel/uapi/drm/amdgpu_drm.h b/libc/kernel/uapi/drm/amdgpu_drm.h
index 6f74fa3..3764d51 100644
--- a/libc/kernel/uapi/drm/amdgpu_drm.h
+++ b/libc/kernel/uapi/drm/amdgpu_drm.h
@@ -467,9 +467,6 @@
 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20
-#define AMDGPU_INFO_VIDEO_CAPS 0x21
-#define AMDGPU_INFO_VIDEO_CAPS_DECODE 0
-#define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1
 #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0)
 #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1)
 #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2)
@@ -484,6 +481,9 @@
 #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11)
 #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12)
 #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13)
+#define AMDGPU_INFO_VIDEO_CAPS 0x21
+#define AMDGPU_INFO_VIDEO_CAPS_DECODE 0
+#define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1
 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
diff --git a/libc/kernel/uapi/drm/drm_fourcc.h b/libc/kernel/uapi/drm/drm_fourcc.h
index aaa94cd..2b5d202 100644
--- a/libc/kernel/uapi/drm/drm_fourcc.h
+++ b/libc/kernel/uapi/drm/drm_fourcc.h
@@ -27,6 +27,8 @@
 #define DRM_FORMAT_INVALID 0
 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ')
 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ')
+#define DRM_FORMAT_R10 fourcc_code('R', '1', '0', ' ')
+#define DRM_FORMAT_R12 fourcc_code('R', '1', '2', ' ')
 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ')
 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8')
 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8')
@@ -145,6 +147,8 @@
 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
 #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a
 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
+#define fourcc_mod_get_vendor(modifier) (((modifier) >> 56) & 0xff)
+#define fourcc_mod_is_vendor(modifier,vendor) (fourcc_mod_get_vendor(modifier) == DRM_FORMAT_MOD_VENDOR_ ##vendor)
 #define fourcc_mod_code(vendor,val) ((((__u64) DRM_FORMAT_MOD_VENDOR_ ##vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
 #define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE
 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
diff --git a/libc/kernel/uapi/drm/i915_drm.h b/libc/kernel/uapi/drm/i915_drm.h
index 9e56f4c..52bfad2 100644
--- a/libc/kernel/uapi/drm/i915_drm.h
+++ b/libc/kernel/uapi/drm/i915_drm.h
@@ -741,6 +741,7 @@
 #define I915_CONTEXT_PARAM_ENGINES 0xa
 #define I915_CONTEXT_PARAM_PERSISTENCE 0xb
 #define I915_CONTEXT_PARAM_RINGSIZE 0xc
+#define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd
   __u64 value;
 };
 struct drm_i915_gem_context_param_sseu {
@@ -774,10 +775,23 @@
 } __attribute__((packed));
 #define I915_DEFINE_CONTEXT_ENGINES_BOND(name__,N__) struct { struct i915_user_extension base; struct i915_engine_class_instance master; __u16 virtual_index; __u16 num_bonds; __u64 flags; __u64 mbz64[4]; struct i915_engine_class_instance engines[N__]; \
 } __attribute__((packed)) name__
+struct i915_context_engines_parallel_submit {
+  struct i915_user_extension base;
+  __u16 engine_index;
+  __u16 width;
+  __u16 num_siblings;
+  __u16 mbz16;
+  __u64 flags;
+  __u64 mbz64[3];
+  struct i915_engine_class_instance engines[0];
+} __packed;
+#define I915_DEFINE_CONTEXT_ENGINES_PARALLEL_SUBMIT(name__,N__) struct { struct i915_user_extension base; __u16 engine_index; __u16 width; __u16 num_siblings; __u16 mbz16; __u64 flags; __u64 mbz64[3]; struct i915_engine_class_instance engines[N__]; \
+} __attribute__((packed)) name__
 struct i915_context_param_engines {
   __u64 extensions;
 #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0
 #define I915_CONTEXT_ENGINES_EXT_BOND 1
+#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2
   struct i915_engine_class_instance engines[0];
 } __attribute__((packed));
 #define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__,N__) struct { __u64 extensions; struct i915_engine_class_instance engines[N__]; \
@@ -907,10 +921,13 @@
   struct i915_engine_class_instance engine;
   __u32 rsvd0;
   __u64 flags;
+#define I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1 << 0)
   __u64 capabilities;
 #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0)
 #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1)
-  __u64 rsvd1[4];
+  __u16 logical_instance;
+  __u16 rsvd1[3];
+  __u64 rsvd2[3];
 };
 struct drm_i915_query_engine_info {
   __u32 num_engines;
@@ -951,6 +968,7 @@
   __u32 handle;
   __u32 flags;
 #define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0
+#define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1
   __u64 extensions;
 };
 struct drm_i915_gem_create_ext_memory_regions {
@@ -959,6 +977,11 @@
   __u32 num_regions;
   __u64 regions;
 };
+struct drm_i915_gem_create_ext_protected_content {
+  struct i915_user_extension base;
+  __u32 flags;
+};
+#define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf
 #ifdef __cplusplus
 }
 #endif
diff --git a/libc/kernel/uapi/drm/mga_drm.h b/libc/kernel/uapi/drm/mga_drm.h
index 4959502..dc62961 100644
--- a/libc/kernel/uapi/drm/mga_drm.h
+++ b/libc/kernel/uapi/drm/mga_drm.h
@@ -175,7 +175,7 @@
     MGA_CLEANUP_DMA = 0x02
   } func;
   unsigned long sarea_priv_offset;
-  int chipset;
+  __struct_group(, always32bit,, int chipset;
   int sgram;
   unsigned int maccess;
   unsigned int fb_cpp;
@@ -185,6 +185,7 @@
   unsigned int depth_offset, depth_pitch;
   unsigned int texture_offset[MGA_NR_TEX_HEAPS];
   unsigned int texture_size[MGA_NR_TEX_HEAPS];
+ );
   unsigned long fb_offset;
   unsigned long mmio_offset;
   unsigned long status_offset;
diff --git a/libc/kernel/uapi/drm/v3d_drm.h b/libc/kernel/uapi/drm/v3d_drm.h
index a393e5d..5887678 100644
--- a/libc/kernel/uapi/drm/v3d_drm.h
+++ b/libc/kernel/uapi/drm/v3d_drm.h
@@ -45,6 +45,35 @@
 #define DRM_IOCTL_V3D_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_DESTROY, struct drm_v3d_perfmon_destroy)
 #define DRM_IOCTL_V3D_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_VALUES, struct drm_v3d_perfmon_get_values)
 #define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x01
+#define DRM_V3D_SUBMIT_EXTENSION 0x02
+struct drm_v3d_extension {
+  __u64 next;
+  __u32 id;
+#define DRM_V3D_EXT_ID_MULTI_SYNC 0x01
+  __u32 flags;
+};
+struct drm_v3d_sem {
+  __u32 handle;
+  __u32 flags;
+  __u64 point;
+  __u64 mbz[2];
+};
+enum v3d_queue {
+  V3D_BIN,
+  V3D_RENDER,
+  V3D_TFU,
+  V3D_CSD,
+  V3D_CACHE_CLEAN,
+};
+struct drm_v3d_multi_sync {
+  struct drm_v3d_extension base;
+  __u64 in_syncs;
+  __u64 out_syncs;
+  __u32 in_sync_count;
+  __u32 out_sync_count;
+  __u32 wait_stage;
+  __u32 pad;
+};
 struct drm_v3d_submit_cl {
   __u32 bcl_start;
   __u32 bcl_end;
@@ -61,6 +90,7 @@
   __u32 flags;
   __u32 perfmon_id;
   __u32 pad;
+  __u64 extensions;
 };
 struct drm_v3d_wait_bo {
   __u32 handle;
@@ -90,6 +120,7 @@
   DRM_V3D_PARAM_SUPPORTS_CSD,
   DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH,
   DRM_V3D_PARAM_SUPPORTS_PERFMON,
+  DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT,
 };
 struct drm_v3d_get_param {
   __u32 param;
@@ -112,6 +143,8 @@
   __u32 bo_handles[4];
   __u32 in_sync;
   __u32 out_sync;
+  __u32 flags;
+  __u64 extensions;
 };
 struct drm_v3d_submit_csd {
   __u32 cfg[7];
@@ -121,6 +154,9 @@
   __u32 in_sync;
   __u32 out_sync;
   __u32 perfmon_id;
+  __u64 extensions;
+  __u32 flags;
+  __u32 pad;
 };
 enum {
   V3D_PERFCNT_FEP_VALID_PRIMTS_NO_PIXELS,
diff --git a/libc/kernel/uapi/drm/virtgpu_drm.h b/libc/kernel/uapi/drm/virtgpu_drm.h
index 842c1fd..342282d 100644
--- a/libc/kernel/uapi/drm/virtgpu_drm.h
+++ b/libc/kernel/uapi/drm/virtgpu_drm.h
@@ -32,9 +32,11 @@
 #define DRM_VIRTGPU_WAIT 0x08
 #define DRM_VIRTGPU_GET_CAPS 0x09
 #define DRM_VIRTGPU_RESOURCE_CREATE_BLOB 0x0a
+#define DRM_VIRTGPU_CONTEXT_INIT 0x0b
 #define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01
 #define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02
-#define VIRTGPU_EXECBUF_FLAGS (VIRTGPU_EXECBUF_FENCE_FD_IN | VIRTGPU_EXECBUF_FENCE_FD_OUT | 0)
+#define VIRTGPU_EXECBUF_RING_IDX 0x04
+#define VIRTGPU_EXECBUF_FLAGS (VIRTGPU_EXECBUF_FENCE_FD_IN | VIRTGPU_EXECBUF_FENCE_FD_OUT | VIRTGPU_EXECBUF_RING_IDX | 0)
 struct drm_virtgpu_map {
   __u64 offset;
   __u32 handle;
@@ -47,12 +49,16 @@
   __u64 bo_handles;
   __u32 num_bo_handles;
   __s32 fence_fd;
+  __u32 ring_idx;
+  __u32 pad;
 };
 #define VIRTGPU_PARAM_3D_FEATURES 1
 #define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2
 #define VIRTGPU_PARAM_RESOURCE_BLOB 3
 #define VIRTGPU_PARAM_HOST_VISIBLE 4
 #define VIRTGPU_PARAM_CROSS_DEVICE 5
+#define VIRTGPU_PARAM_CONTEXT_INIT 6
+#define VIRTGPU_PARAM_SUPPORTED_CAPSET_IDs 7
 struct drm_virtgpu_getparam {
   __u64 param;
   __u64 value;
@@ -132,6 +138,19 @@
   __u64 cmd;
   __u64 blob_id;
 };
+#define VIRTGPU_CONTEXT_PARAM_CAPSET_ID 0x0001
+#define VIRTGPU_CONTEXT_PARAM_NUM_RINGS 0x0002
+#define VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK 0x0003
+struct drm_virtgpu_context_set_param {
+  __u64 param;
+  __u64 value;
+};
+struct drm_virtgpu_context_init {
+  __u32 num_params;
+  __u32 pad;
+  __u64 ctx_set_params;
+};
+#define VIRTGPU_EVENT_FENCE_SIGNALED 0x90000000
 #define DRM_IOCTL_VIRTGPU_MAP DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
 #define DRM_IOCTL_VIRTGPU_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER, struct drm_virtgpu_execbuffer)
 #define DRM_IOCTL_VIRTGPU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM, struct drm_virtgpu_getparam)
@@ -142,6 +161,7 @@
 #define DRM_IOCTL_VIRTGPU_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, struct drm_virtgpu_3d_wait)
 #define DRM_IOCTL_VIRTGPU_GET_CAPS DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, struct drm_virtgpu_get_caps)
 #define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE_BLOB DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE_BLOB, struct drm_virtgpu_resource_create_blob)
+#define DRM_IOCTL_VIRTGPU_CONTEXT_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_CONTEXT_INIT, struct drm_virtgpu_context_init)
 #ifdef __cplusplus
 }
 #endif