diff --git a/libc/kernel/uapi/drm/amdgpu_drm.h b/libc/kernel/uapi/drm/amdgpu_drm.h
index 59f5260..bdf59d6 100644
--- a/libc/kernel/uapi/drm/amdgpu_drm.h
+++ b/libc/kernel/uapi/drm/amdgpu_drm.h
@@ -59,6 +59,7 @@
 #define AMDGPU_GEM_DOMAIN_GDS 0x8
 #define AMDGPU_GEM_DOMAIN_GWS 0x10
 #define AMDGPU_GEM_DOMAIN_OA 0x20
+#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)
 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
@@ -67,6 +68,7 @@
 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)
+#define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8)
 struct drm_amdgpu_gem_create_in {
   __u64 bo_size;
   __u64 alignment;
@@ -305,13 +307,15 @@
 #define AMDGPU_HW_IP_UVD_ENC 5
 #define AMDGPU_HW_IP_VCN_DEC 6
 #define AMDGPU_HW_IP_VCN_ENC 7
-#define AMDGPU_HW_IP_NUM 8
+#define AMDGPU_HW_IP_VCN_JPEG 8
+#define AMDGPU_HW_IP_NUM 9
 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
 #define AMDGPU_CHUNK_ID_IB 0x01
 #define AMDGPU_CHUNK_ID_FENCE 0x02
 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
+#define AMDGPU_CHUNK_ID_BO_HANDLES 0x06
 struct drm_amdgpu_cs_chunk {
   __u32 chunk_id;
   __u32 length_dw;
@@ -334,6 +338,7 @@
 #define AMDGPU_IB_FLAG_CE (1 << 0)
 #define AMDGPU_IB_FLAG_PREAMBLE (1 << 1)
 #define AMDGPU_IB_FLAG_PREEMPT (1 << 2)
+#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
 struct drm_amdgpu_cs_chunk_ib {
   __u32 _pad;
   __u32 flags;
@@ -397,6 +402,9 @@
 #define AMDGPU_INFO_FW_SOS 0x0c
 #define AMDGPU_INFO_FW_ASD 0x0d
 #define AMDGPU_INFO_FW_VCN 0x0e
+#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f
+#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
+#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
 #define AMDGPU_INFO_VRAM_USAGE 0x10
 #define AMDGPU_INFO_GTT_USAGE 0x11
diff --git a/libc/kernel/uapi/drm/drm.h b/libc/kernel/uapi/drm/drm.h
index ec0c1fa..21f23f4 100644
--- a/libc/kernel/uapi/drm/drm.h
+++ b/libc/kernel/uapi/drm/drm.h
@@ -369,6 +369,8 @@
 #define DRM_CLIENT_CAP_STEREO_3D 1
 #define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2
 #define DRM_CLIENT_CAP_ATOMIC 3
+#define DRM_CLIENT_CAP_ASPECT_RATIO 4
+#define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5
 struct drm_set_client_cap {
   __u64 capability;
   __u64 value;
diff --git a/libc/kernel/uapi/drm/drm_fourcc.h b/libc/kernel/uapi/drm/drm_fourcc.h
index d5fb055..9634e99 100644
--- a/libc/kernel/uapi/drm/drm_fourcc.h
+++ b/libc/kernel/uapi/drm/drm_fourcc.h
@@ -106,6 +106,7 @@
 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
+#define DRM_FORMAT_MOD_VENDOR_ARM 0x08
 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
 #define fourcc_mod_code(vendor,val) ((((__u64) DRM_FORMAT_MOD_VENDOR_ ##vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
@@ -116,6 +117,7 @@
 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
+#define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
@@ -128,7 +130,31 @@
 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB fourcc_mod_code(NVIDIA, 0x13)
 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB fourcc_mod_code(NVIDIA, 0x14)
 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB fourcc_mod_code(NVIDIA, 0x15)
+#define __fourcc_mod_broadcom_param_shift 8
+#define __fourcc_mod_broadcom_param_bits 48
+#define fourcc_mod_broadcom_code(val,params) fourcc_mod_code(BROADCOM, ((((__u64) params) << __fourcc_mod_broadcom_param_shift) | val))
+#define fourcc_mod_broadcom_param(m) ((int) (((m) >> __fourcc_mod_broadcom_param_shift) & ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
+#define fourcc_mod_broadcom_mod(m) ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << __fourcc_mod_broadcom_param_shift))
 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
+#define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) fourcc_mod_broadcom_code(2, v)
+#define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) fourcc_mod_broadcom_code(3, v)
+#define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) fourcc_mod_broadcom_code(4, v)
+#define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) fourcc_mod_broadcom_code(5, v)
+#define DRM_FORMAT_MOD_BROADCOM_SAND32 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
+#define DRM_FORMAT_MOD_BROADCOM_SAND64 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
+#define DRM_FORMAT_MOD_BROADCOM_SAND128 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
+#define DRM_FORMAT_MOD_BROADCOM_SAND256 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
+#define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
+#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode)
+#define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf
+#define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
+#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)
+#define AFBC_FORMAT_MOD_YTR (1ULL << 4)
+#define AFBC_FORMAT_MOD_SPLIT (1ULL << 5)
+#define AFBC_FORMAT_MOD_SPARSE (1ULL << 6)
+#define AFBC_FORMAT_MOD_CBR (1ULL << 7)
+#define AFBC_FORMAT_MOD_TILED (1ULL << 8)
+#define AFBC_FORMAT_MOD_SC (1ULL << 9)
 #ifdef __cplusplus
 #endif
 #endif
diff --git a/libc/kernel/uapi/drm/drm_mode.h b/libc/kernel/uapi/drm/drm_mode.h
index b91f161..06c26e4 100644
--- a/libc/kernel/uapi/drm/drm_mode.h
+++ b/libc/kernel/uapi/drm/drm_mode.h
@@ -60,10 +60,19 @@
 #define DRM_MODE_PICTURE_ASPECT_NONE 0
 #define DRM_MODE_PICTURE_ASPECT_4_3 1
 #define DRM_MODE_PICTURE_ASPECT_16_9 2
+#define DRM_MODE_PICTURE_ASPECT_64_27 3
+#define DRM_MODE_PICTURE_ASPECT_256_135 4
+#define DRM_MODE_CONTENT_TYPE_NO_DATA 0
+#define DRM_MODE_CONTENT_TYPE_GRAPHICS 1
+#define DRM_MODE_CONTENT_TYPE_PHOTO 2
+#define DRM_MODE_CONTENT_TYPE_CINEMA 3
+#define DRM_MODE_CONTENT_TYPE_GAME 4
 #define DRM_MODE_FLAG_PIC_AR_MASK (0x0F << 19)
 #define DRM_MODE_FLAG_PIC_AR_NONE (DRM_MODE_PICTURE_ASPECT_NONE << 19)
 #define DRM_MODE_FLAG_PIC_AR_4_3 (DRM_MODE_PICTURE_ASPECT_4_3 << 19)
 #define DRM_MODE_FLAG_PIC_AR_16_9 (DRM_MODE_PICTURE_ASPECT_16_9 << 19)
+#define DRM_MODE_FLAG_PIC_AR_64_27 (DRM_MODE_PICTURE_ASPECT_64_27 << 19)
+#define DRM_MODE_FLAG_PIC_AR_256_135 (DRM_MODE_PICTURE_ASPECT_256_135 << 19)
 #define DRM_MODE_FLAG_ALL (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLSCAN | DRM_MODE_FLAG_CSYNC | DRM_MODE_FLAG_PCSYNC | DRM_MODE_FLAG_NCSYNC | DRM_MODE_FLAG_HSKEW | DRM_MODE_FLAG_DBLCLK | DRM_MODE_FLAG_CLKDIV2 | DRM_MODE_FLAG_3D_MASK)
 #define DRM_MODE_DPMS_ON 0
 #define DRM_MODE_DPMS_STANDBY 1
@@ -207,6 +216,7 @@
 #define DRM_MODE_CONNECTOR_VIRTUAL 15
 #define DRM_MODE_CONNECTOR_DSI 16
 #define DRM_MODE_CONNECTOR_DPI 17
+#define DRM_MODE_CONNECTOR_WRITEBACK 18
 struct drm_mode_get_connector {
   __u64 encoders_ptr;
   __u64 modes_ptr;
diff --git a/libc/kernel/uapi/drm/exynos_drm.h b/libc/kernel/uapi/drm/exynos_drm.h
index ed9022b..8b27cbb 100644
--- a/libc/kernel/uapi/drm/exynos_drm.h
+++ b/libc/kernel/uapi/drm/exynos_drm.h
@@ -80,6 +80,109 @@
 struct drm_exynos_g2d_exec {
   __u64 async;
 };
+struct drm_exynos_ioctl_ipp_get_res {
+  __u32 count_ipps;
+  __u32 reserved;
+  __u64 ipp_id_ptr;
+};
+enum drm_exynos_ipp_format_type {
+  DRM_EXYNOS_IPP_FORMAT_SOURCE = 0x01,
+  DRM_EXYNOS_IPP_FORMAT_DESTINATION = 0x02,
+};
+struct drm_exynos_ipp_format {
+  __u32 fourcc;
+  __u32 type;
+  __u64 modifier;
+};
+enum drm_exynos_ipp_capability {
+  DRM_EXYNOS_IPP_CAP_CROP = 0x01,
+  DRM_EXYNOS_IPP_CAP_ROTATE = 0x02,
+  DRM_EXYNOS_IPP_CAP_SCALE = 0x04,
+  DRM_EXYNOS_IPP_CAP_CONVERT = 0x08,
+};
+struct drm_exynos_ioctl_ipp_get_caps {
+  __u32 ipp_id;
+  __u32 capabilities;
+  __u32 reserved;
+  __u32 formats_count;
+  __u64 formats_ptr;
+};
+enum drm_exynos_ipp_limit_type {
+  DRM_EXYNOS_IPP_LIMIT_TYPE_SIZE = 0x0001,
+  DRM_EXYNOS_IPP_LIMIT_TYPE_SCALE = 0x0002,
+  DRM_EXYNOS_IPP_LIMIT_SIZE_BUFFER = 0x0001 << 16,
+  DRM_EXYNOS_IPP_LIMIT_SIZE_AREA = 0x0002 << 16,
+  DRM_EXYNOS_IPP_LIMIT_SIZE_ROTATED = 0x0003 << 16,
+  DRM_EXYNOS_IPP_LIMIT_TYPE_MASK = 0x000f,
+  DRM_EXYNOS_IPP_LIMIT_SIZE_MASK = 0x000f << 16,
+};
+struct drm_exynos_ipp_limit_val {
+  __u32 min;
+  __u32 max;
+  __u32 align;
+  __u32 reserved;
+};
+struct drm_exynos_ipp_limit {
+  __u32 type;
+  __u32 reserved;
+  struct drm_exynos_ipp_limit_val h;
+  struct drm_exynos_ipp_limit_val v;
+};
+struct drm_exynos_ioctl_ipp_get_limits {
+  __u32 ipp_id;
+  __u32 fourcc;
+  __u64 modifier;
+  __u32 type;
+  __u32 limits_count;
+  __u64 limits_ptr;
+};
+enum drm_exynos_ipp_task_id {
+  DRM_EXYNOS_IPP_TASK_BUFFER = 0x0001,
+  DRM_EXYNOS_IPP_TASK_RECTANGLE = 0x0002,
+  DRM_EXYNOS_IPP_TASK_TRANSFORM = 0x0003,
+  DRM_EXYNOS_IPP_TASK_ALPHA = 0x0004,
+  DRM_EXYNOS_IPP_TASK_TYPE_SOURCE = 0x0001 << 16,
+  DRM_EXYNOS_IPP_TASK_TYPE_DESTINATION = 0x0002 << 16,
+};
+struct drm_exynos_ipp_task_buffer {
+  __u32 id;
+  __u32 fourcc;
+  __u32 width, height;
+  __u32 gem_id[4];
+  __u32 offset[4];
+  __u32 pitch[4];
+  __u64 modifier;
+};
+struct drm_exynos_ipp_task_rect {
+  __u32 id;
+  __u32 reserved;
+  __u32 x;
+  __u32 y;
+  __u32 w;
+  __u32 h;
+};
+struct drm_exynos_ipp_task_transform {
+  __u32 id;
+  __u32 rotation;
+};
+struct drm_exynos_ipp_task_alpha {
+  __u32 id;
+  __u32 value;
+};
+enum drm_exynos_ipp_flag {
+  DRM_EXYNOS_IPP_FLAG_EVENT = 0x01,
+  DRM_EXYNOS_IPP_FLAG_TEST_ONLY = 0x02,
+  DRM_EXYNOS_IPP_FLAG_NONBLOCK = 0x04,
+};
+#define DRM_EXYNOS_IPP_FLAGS (DRM_EXYNOS_IPP_FLAG_EVENT | DRM_EXYNOS_IPP_FLAG_TEST_ONLY | DRM_EXYNOS_IPP_FLAG_NONBLOCK)
+struct drm_exynos_ioctl_ipp_commit {
+  __u32 ipp_id;
+  __u32 flags;
+  __u32 reserved;
+  __u32 params_size;
+  __u64 params_ptr;
+  __u64 user_data;
+};
 #define DRM_EXYNOS_GEM_CREATE 0x00
 #define DRM_EXYNOS_GEM_MAP 0x01
 #define DRM_EXYNOS_GEM_GET 0x04
@@ -87,6 +190,10 @@
 #define DRM_EXYNOS_G2D_GET_VER 0x20
 #define DRM_EXYNOS_G2D_SET_CMDLIST 0x21
 #define DRM_EXYNOS_G2D_EXEC 0x22
+#define DRM_EXYNOS_IPP_GET_RESOURCES 0x40
+#define DRM_EXYNOS_IPP_GET_CAPS 0x41
+#define DRM_EXYNOS_IPP_GET_LIMITS 0x42
+#define DRM_EXYNOS_IPP_COMMIT 0x43
 #define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
 #define DRM_IOCTL_EXYNOS_GEM_MAP DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_MAP, struct drm_exynos_gem_map)
 #define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info)
@@ -94,7 +201,12 @@
 #define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver)
 #define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist)
 #define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
+#define DRM_IOCTL_EXYNOS_IPP_GET_RESOURCES DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_GET_RESOURCES, struct drm_exynos_ioctl_ipp_get_res)
+#define DRM_IOCTL_EXYNOS_IPP_GET_CAPS DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_GET_CAPS, struct drm_exynos_ioctl_ipp_get_caps)
+#define DRM_IOCTL_EXYNOS_IPP_GET_LIMITS DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_GET_LIMITS, struct drm_exynos_ioctl_ipp_get_limits)
+#define DRM_IOCTL_EXYNOS_IPP_COMMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_COMMIT, struct drm_exynos_ioctl_ipp_commit)
 #define DRM_EXYNOS_G2D_EVENT 0x80000000
+#define DRM_EXYNOS_IPP_EVENT 0x80000002
 struct drm_exynos_g2d_event {
   struct drm_event base;
   __u64 user_data;
@@ -103,6 +215,15 @@
   __u32 cmdlist_no;
   __u32 reserved;
 };
+struct drm_exynos_ipp_event {
+  struct drm_event base;
+  __u64 user_data;
+  __u32 tv_sec;
+  __u32 tv_usec;
+  __u32 ipp_id;
+  __u32 sequence;
+  __u64 reserved;
+};
 #ifdef __cplusplus
 #endif
 #endif
diff --git a/libc/kernel/uapi/drm/tegra_drm.h b/libc/kernel/uapi/drm/tegra_drm.h
index e0bcf95..ee111dc 100644
--- a/libc/kernel/uapi/drm/tegra_drm.h
+++ b/libc/kernel/uapi/drm/tegra_drm.h
@@ -154,7 +154,7 @@
 #define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
 #define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
 #define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
-#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel)
+#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_close_channel)
 #define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
 #define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
 #define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base)
diff --git a/libc/kernel/uapi/drm/v3d_drm.h b/libc/kernel/uapi/drm/v3d_drm.h
new file mode 100644
index 0000000..c3e58cb
--- /dev/null
+++ b/libc/kernel/uapi/drm/v3d_drm.h
@@ -0,0 +1,87 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ***   To edit the content of this header, modify the corresponding
+ ***   source file (e.g. under external/kernel-headers/original/) then
+ ***   run bionic/libc/kernel/tools/update_all.py
+ ***
+ ***   Any manual change here will be lost the next time this script will
+ ***   be run. You've been warned!
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef _V3D_DRM_H_
+#define _V3D_DRM_H_
+#include "drm.h"
+#ifdef __cplusplus
+#endif
+#define DRM_V3D_SUBMIT_CL 0x00
+#define DRM_V3D_WAIT_BO 0x01
+#define DRM_V3D_CREATE_BO 0x02
+#define DRM_V3D_MMAP_BO 0x03
+#define DRM_V3D_GET_PARAM 0x04
+#define DRM_V3D_GET_BO_OFFSET 0x05
+#define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
+#define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
+#define DRM_IOCTL_V3D_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_CREATE_BO, struct drm_v3d_create_bo)
+#define DRM_IOCTL_V3D_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
+#define DRM_IOCTL_V3D_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
+#define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
+struct drm_v3d_submit_cl {
+  __u32 bcl_start;
+  __u32 bcl_end;
+  __u32 rcl_start;
+  __u32 rcl_end;
+  __u32 in_sync_bcl;
+  __u32 in_sync_rcl;
+  __u32 out_sync;
+  __u32 qma;
+  __u32 qms;
+  __u32 qts;
+  __u64 bo_handles;
+  __u32 bo_handle_count;
+  __u32 pad;
+};
+struct drm_v3d_wait_bo {
+  __u32 handle;
+  __u32 pad;
+  __u64 timeout_ns;
+};
+struct drm_v3d_create_bo {
+  __u32 size;
+  __u32 flags;
+  __u32 handle;
+  __u32 offset;
+};
+struct drm_v3d_mmap_bo {
+  __u32 handle;
+  __u32 flags;
+  __u64 offset;
+};
+enum drm_v3d_param {
+  DRM_V3D_PARAM_V3D_UIFCFG,
+  DRM_V3D_PARAM_V3D_HUB_IDENT1,
+  DRM_V3D_PARAM_V3D_HUB_IDENT2,
+  DRM_V3D_PARAM_V3D_HUB_IDENT3,
+  DRM_V3D_PARAM_V3D_CORE0_IDENT0,
+  DRM_V3D_PARAM_V3D_CORE0_IDENT1,
+  DRM_V3D_PARAM_V3D_CORE0_IDENT2,
+};
+struct drm_v3d_get_param {
+  __u32 param;
+  __u32 pad;
+  __u64 value;
+};
+struct drm_v3d_get_bo_offset {
+  __u32 handle;
+  __u32 offset;
+};
+#ifdef __cplusplus
+#endif
+#endif
diff --git a/libc/kernel/uapi/drm/vc4_drm.h b/libc/kernel/uapi/drm/vc4_drm.h
index 05ed172..29eb872 100644
--- a/libc/kernel/uapi/drm/vc4_drm.h
+++ b/libc/kernel/uapi/drm/vc4_drm.h
@@ -91,6 +91,8 @@
   __u32 flags;
   __u64 seqno;
   __u32 perfmonid;
+  __u32 in_sync;
+  __u32 out_sync;
   __u32 pad2;
 };
 struct drm_vc4_wait_seqno {
diff --git a/libc/kernel/uapi/drm/vmwgfx_drm.h b/libc/kernel/uapi/drm/vmwgfx_drm.h
index f6a7b14..7df722a 100644
--- a/libc/kernel/uapi/drm/vmwgfx_drm.h
+++ b/libc/kernel/uapi/drm/vmwgfx_drm.h
@@ -25,6 +25,7 @@
 #define DRM_VMW_MAX_MIP_LEVELS 24
 #define DRM_VMW_GET_PARAM 0
 #define DRM_VMW_ALLOC_DMABUF 1
+#define DRM_VMW_ALLOC_BO 1
 #define DRM_VMW_UNREF_DMABUF 2
 #define DRM_VMW_HANDLE_CLOSE 2
 #define DRM_VMW_CURSOR_BYPASS 3
@@ -51,6 +52,8 @@
 #define DRM_VMW_GB_SURFACE_REF 24
 #define DRM_VMW_SYNCCPU 25
 #define DRM_VMW_CREATE_EXTENDED_CONTEXT 26
+#define DRM_VMW_GB_SURFACE_CREATE_EXT 27
+#define DRM_VMW_GB_SURFACE_REF_EXT 28
 #define DRM_VMW_PARAM_NUM_STREAMS 0
 #define DRM_VMW_PARAM_NUM_FREE_STREAMS 1
 #define DRM_VMW_PARAM_3D 2
@@ -64,6 +67,8 @@
 #define DRM_VMW_PARAM_MAX_MOB_SIZE 10
 #define DRM_VMW_PARAM_SCREEN_TARGET 11
 #define DRM_VMW_PARAM_DX 12
+#define DRM_VMW_PARAM_HW_CAPS2 13
+#define DRM_VMW_PARAM_SM4_1 14
 enum drm_vmw_handle_type {
   DRM_VMW_HANDLE_LEGACY = 0,
   DRM_VMW_HANDLE_PRIME = 1
@@ -124,25 +129,24 @@
   __s32 fd;
   __s32 error;
 };
-struct drm_vmw_alloc_dmabuf_req {
+struct drm_vmw_alloc_bo_req {
   __u32 size;
   __u32 pad64;
 };
-struct drm_vmw_dmabuf_rep {
+#define drm_vmw_alloc_dmabuf_req drm_vmw_alloc_bo_req
+struct drm_vmw_bo_rep {
   __u64 map_handle;
   __u32 handle;
   __u32 cur_gmr_id;
   __u32 cur_gmr_offset;
   __u32 pad64;
 };
-union drm_vmw_alloc_dmabuf_arg {
-  struct drm_vmw_alloc_dmabuf_req req;
-  struct drm_vmw_dmabuf_rep rep;
+#define drm_vmw_dmabuf_rep drm_vmw_bo_rep
+union drm_vmw_alloc_bo_arg {
+  struct drm_vmw_alloc_bo_req req;
+  struct drm_vmw_bo_rep rep;
 };
-struct drm_vmw_unref_dmabuf_arg {
-  __u32 handle;
-  __u32 pad64;
-};
+#define drm_vmw_alloc_dmabuf_arg drm_vmw_alloc_bo_arg
 struct drm_vmw_rect {
   __s32 x;
   __s32 y;
@@ -321,6 +325,30 @@
   __u32 handle;
   __u32 pad64;
 };
+#define drm_vmw_unref_dmabuf_arg drm_vmw_handle_close_arg
+enum drm_vmw_surface_version {
+  drm_vmw_gb_surface_v1
+};
+struct drm_vmw_gb_surface_create_ext_req {
+  struct drm_vmw_gb_surface_create_req base;
+  enum drm_vmw_surface_version version;
+  uint32_t svga3d_flags_upper_32_bits;
+  SVGA3dMSPattern multisample_pattern;
+  SVGA3dMSQualityLevel quality_level;
+  uint64_t must_be_zero;
+};
+union drm_vmw_gb_surface_create_ext_arg {
+  struct drm_vmw_gb_surface_create_rep rep;
+  struct drm_vmw_gb_surface_create_ext_req req;
+};
+struct drm_vmw_gb_surface_ref_ext_rep {
+  struct drm_vmw_gb_surface_create_ext_req creq;
+  struct drm_vmw_gb_surface_create_rep crep;
+};
+union drm_vmw_gb_surface_reference_ext_arg {
+  struct drm_vmw_gb_surface_ref_ext_rep rep;
+  struct drm_vmw_surface_arg req;
+};
 #ifdef __cplusplus
 #endif
 #endif