commit 9abbbdc5346020e33a8fdbe7254dd0fdff9df616
author Elliott Hughes <enh@google.com> Wed Feb 19 14:54:31 2014 -0800
committer Elliott Hughes <enh@google.com> Wed Feb 19 14:54:31 2014 -0800
tree 9a4c06c1cb4b09c8c957c72e061984db2321cc40
parent e6c451f5f2e17fccccedaa1c2a90d8d9ba0c1917

Make mips/mips64 syscall stubs more like the other architectures.

Change-Id: I55f8c1a95f643a6e484f12fbcc25e2c77e55b6b8

libc/arch-mips/syscalls/_flush_cache.S

diff --git a/libc/arch-mips/syscalls/_flush_cache.S b/libc/arch-mips/syscalls/_flush_cache.S
index 1d14843..64967fe 100644
--- a/libc/arch-mips/syscalls/_flush_cache.S
+++ b/libc/arch-mips/syscalls/_flush_cache.S
@@ -1,14 +1,8 @@
 /* Generated by gensyscalls.py. Do not edit. */
 
-#include <asm/unistd.h>
-#include <machine/asm.h>
-#include <machine/regdef.h>
-    .text
-    .globl _flush_cache
-    .align 4
-    .ent _flush_cache
+#include <private/bionic_asm.h>
 
-_flush_cache:
+ENTRY(_flush_cache)
     .set noreorder
     .cpload t9
     li v0, __NR_cacheflush
@@ -22,4 +16,4 @@
     j t9
     nop
     .set reorder
-    .end _flush_cache
+END(_flush_cache)