diff --git a/libc/kernel/uapi/rdma/mlx5-abi.h b/libc/kernel/uapi/rdma/mlx5-abi.h
index b51ff4e..9347cf3 100644
--- a/libc/kernel/uapi/rdma/mlx5-abi.h
+++ b/libc/kernel/uapi/rdma/mlx5-abi.h
@@ -23,6 +23,7 @@
 enum {
   MLX5_QP_FLAG_SIGNATURE = 1 << 0,
   MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
+  MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2,
 };
 enum {
   MLX5_SRQ_FLAG_SIGNATURE = 1 << 0,
@@ -126,6 +127,23 @@
   __u32 sw_parsing_offloads;
   __u32 supported_qpts;
 };
+struct mlx5_ib_striding_rq_caps {
+  __u32 min_single_stride_log_num_of_bytes;
+  __u32 max_single_stride_log_num_of_bytes;
+  __u32 min_single_wqe_log_num_of_strides;
+  __u32 max_single_wqe_log_num_of_strides;
+  __u32 supported_qpts;
+  __u32 reserved;
+};
+enum mlx5_ib_query_dev_resp_flags {
+  MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0,
+  MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1,
+};
+enum mlx5_ib_tunnel_offloads {
+  MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0,
+  MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1,
+  MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2
+};
 struct mlx5_ib_query_device_resp {
   __u32 comp_mask;
   __u32 response_length;
@@ -134,8 +152,14 @@
   struct mlx5_ib_cqe_comp_caps cqe_comp_caps;
   struct mlx5_packet_pacing_caps packet_pacing_caps;
   __u32 mlx5_ib_support_multi_pkt_send_wqes;
-  __u32 reserved;
+  __u32 flags;
   struct mlx5_ib_sw_parsing_caps sw_parsing_caps;
+  struct mlx5_ib_striding_rq_caps striding_rq_caps;
+  __u32 tunnel_offloads_caps;
+  __u32 reserved;
+};
+enum mlx5_ib_create_cq_flags {
+  MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0,
 };
 struct mlx5_ib_create_cq {
   __u64 buf_addr;
@@ -143,7 +167,7 @@
   __u32 cqe_size;
   __u8 cqe_comp_en;
   __u8 cqe_comp_res_format;
-  __u16 reserved;
+  __u16 flags;
 };
 struct mlx5_ib_create_cq_resp {
   __u32 cqn;
@@ -189,7 +213,8 @@
   MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4,
   MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
   MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
-  MLX5_RX_HASH_DST_PORT_UDP = 1 << 7
+  MLX5_RX_HASH_DST_PORT_UDP = 1 << 7,
+  MLX5_RX_HASH_INNER = 1 << 31
 };
 struct mlx5_ib_create_qp_rss {
   __u64 rx_hash_fields_mask;
@@ -198,7 +223,7 @@
   __u8 reserved[6];
   __u8 rx_hash_key[128];
   __u32 comp_mask;
-  __u32 reserved1;
+  __u32 flags;
 };
 struct mlx5_ib_create_qp_resp {
   __u32 bfreg_index;
@@ -209,6 +234,9 @@
   __u8 reserved1;
   __u16 reserved2;
 };
+enum mlx5_ib_create_wq_mask {
+  MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0),
+};
 struct mlx5_ib_create_wq {
   __u64 buf_addr;
   __u64 db_addr;
@@ -217,7 +245,9 @@
   __u32 user_index;
   __u32 flags;
   __u32 comp_mask;
-  __u32 reserved;
+  __u32 single_stride_log_num_of_bytes;
+  __u32 single_wqe_log_num_of_strides;
+  __u32 two_byte_shift_en;
 };
 struct mlx5_ib_create_ah_resp {
   __u32 response_length;