Rewrite <fenv.h> for ARM.
The old code was one big no-op.
Bug: http://code.google.com/p/android/issues/detail?id=38196
Change-Id: I201a6ffa477385b2629f45e8c948bdfbd47b5bf1
diff --git a/libm/include/arm/fenv.h b/libm/include/arm/fenv.h
index da7e696..a96f99e 100644
--- a/libm/include/arm/fenv.h
+++ b/libm/include/arm/fenv.h
@@ -26,193 +26,151 @@
* $FreeBSD: src/lib/msun/arm/fenv.h,v 1.5 2005/03/16 19:03:45 das Exp $
*/
-#ifndef _FENV_H_
-#define _FENV_H_
+/*
+ * Rewritten for Android.
+ *
+ * The ARM FPSCR is described here:
+ * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344b/Chdfafia.html
+ */
+
+#ifndef _FENV_H_
+#define _FENV_H_
#include <sys/types.h>
__BEGIN_DECLS
-typedef __uint32_t fenv_t;
-typedef __uint32_t fexcept_t;
+typedef __uint32_t fenv_t;
+typedef __uint32_t fexcept_t;
-/* Exception flags */
-#define FE_INVALID 0x0001
-#define FE_DIVBYZERO 0x0002
-#define FE_OVERFLOW 0x0004
-#define FE_UNDERFLOW 0x0008
-#define FE_INEXACT 0x0010
-#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \
- FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW)
+/* Exception flags. */
+#define FE_INVALID 0x01
+#define FE_DIVBYZERO 0x02
+#define FE_OVERFLOW 0x04
+#define FE_UNDERFLOW 0x08
+#define FE_INEXACT 0x10
+#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW)
+#define _FPSCR_ENABLE_SHIFT 8
+#define _FPSCR_ENABLE_MASK (FE_ALL_EXCEPT << _FPSCR_ENABLE_SHIFT)
-/* Rounding modes */
-#define FE_TONEAREST 0x0000
-#define FE_TOWARDZERO 0x0001
-#define FE_UPWARD 0x0002
-#define FE_DOWNWARD 0x0003
-#define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \
- FE_UPWARD | FE_TOWARDZERO)
+/* Rounding modes. */
+#define FE_TONEAREST 0x0
+#define FE_UPWARD 0x1
+#define FE_DOWNWARD 0x2
+#define FE_TOWARDZERO 0x3
+#define _FPSCR_RMODE_SHIFT 22
-/* Default floating-point environment */
-extern const fenv_t __fe_dfl_env;
-#define FE_DFL_ENV (&__fe_dfl_env)
+/* Default floating-point environment. */
+extern const fenv_t __fe_dfl_env;
+#define FE_DFL_ENV (&__fe_dfl_env)
-/* We need to be able to map status flag positions to mask flag positions */
-#define _FPUSW_SHIFT 16
-#define _ENABLE_MASK (FE_ALL_EXCEPT << _FPUSW_SHIFT)
-
-#ifdef ARM_HARD_FLOAT
-#define __rfs(__fpsr) __asm __volatile("rfs %0" : "=r" (*(__fpsr)))
-#define __wfs(__fpsr) __asm __volatile("wfs %0" : : "r" (__fpsr))
-#else
-#define __rfs(__fpsr)
-#define __wfs(__fpsr)
-#endif
-
-static __inline int
-feclearexcept(int __excepts)
-{
- fexcept_t __fpsr;
-
- __rfs(&__fpsr);
- __fpsr &= ~__excepts;
- __wfs(__fpsr);
- return (0);
+static __inline int fegetenv(fenv_t* __envp) {
+ fenv_t _fpscr;
+ __asm__ __volatile__("vmrs %0,fpscr" : "=r" (_fpscr));
+ *__envp = _fpscr;
+ return 0;
}
-static __inline int
-fegetexceptflag(fexcept_t *__flagp, int __excepts)
-{
- fexcept_t __fpsr;
-
- __rfs(&__fpsr);
- *__flagp = __fpsr & __excepts;
- return (0);
+static __inline int fesetenv(const fenv_t* __envp) {
+ fenv_t _fpscr = *__envp;
+ __asm__ __volatile__("vmsr fpscr,%0" : :"ri" (_fpscr));
+ return 0;
}
-static __inline int
-fesetexceptflag(const fexcept_t *__flagp, int __excepts)
-{
- fexcept_t __fpsr;
-
- __rfs(&__fpsr);
- __fpsr &= ~__excepts;
- __fpsr |= *__flagp & __excepts;
- __wfs(__fpsr);
- return (0);
+static __inline int feclearexcept(int __excepts) {
+ fexcept_t __fpscr;
+ fegetenv(&__fpscr);
+ __fpscr &= ~__excepts;
+ fesetenv(&__fpscr);
+ return 0;
}
-static __inline int
-feraiseexcept(int __excepts)
-{
- fexcept_t __ex = __excepts;
-
- fesetexceptflag(&__ex, __excepts); /* XXX */
- return (0);
+static __inline int fegetexceptflag(fexcept_t* __flagp, int __excepts) {
+ fexcept_t __fpscr;
+ fegetenv(&__fpscr);
+ *__flagp = __fpscr & __excepts;
+ return 0;
}
-static __inline int
-fetestexcept(int __excepts)
-{
- fexcept_t __fpsr;
-
- __rfs(&__fpsr);
- return (__fpsr & __excepts);
+static __inline int fesetexceptflag(const fexcept_t* __flagp, int __excepts) {
+ fexcept_t __fpscr;
+ fegetenv(&__fpscr);
+ __fpscr &= ~__excepts;
+ __fpscr |= *__flagp & __excepts;
+ fesetenv(&__fpscr);
+ return 0;
}
-static __inline int
-fegetround(void)
-{
-
- /*
- * Apparently, the rounding mode is specified as part of the
- * instruction format on ARM, so the dynamic rounding mode is
- * indeterminate. Some FPUs may differ.
- */
- return (-1);
+static __inline int feraiseexcept(int __excepts) {
+ fexcept_t __ex = __excepts;
+ fesetexceptflag(&__ex, __excepts);
+ return 0;
}
-static __inline int
-fesetround(int __round)
-{
-
- return (-1);
+static __inline int fetestexcept(int __excepts) {
+ fexcept_t __fpscr;
+ fegetenv(&__fpscr);
+ return (__fpscr & __excepts);
}
-static __inline int
-fegetenv(fenv_t *__envp)
-{
-
- __rfs(__envp);
- return (0);
+static __inline int fegetround(void) {
+ fenv_t _fpscr;
+ fegetenv(&_fpscr);
+ return ((_fpscr >> _FPSCR_RMODE_SHIFT) & 0x3);
}
-static __inline int
-feholdexcept(fenv_t *__envp)
-{
- fenv_t __env;
-
- __rfs(&__env);
- *__envp = __env;
- __env &= ~(FE_ALL_EXCEPT | _ENABLE_MASK);
- __wfs(__env);
- return (0);
+static __inline int fesetround(int __round) {
+ fenv_t _fpscr;
+ fegetenv(&_fpscr);
+ _fpscr &= ~(0x3 << _FPSCR_RMODE_SHIFT);
+ _fpscr |= (__round << _FPSCR_RMODE_SHIFT);
+ fesetenv(&_fpscr);
+ return 0;
}
-static __inline int
-fesetenv(const fenv_t *__envp)
-{
-
- __wfs(*__envp);
- return (0);
+static __inline int feholdexcept(fenv_t* __envp) {
+ fenv_t __env;
+ fegetenv(&__env);
+ *__envp = __env;
+ __env &= ~(FE_ALL_EXCEPT | _FPSCR_ENABLE_MASK);
+ fesetenv(&__env);
+ return 0;
}
-static __inline int
-feupdateenv(const fenv_t *__envp)
-{
- fexcept_t __fpsr;
-
- __rfs(&__fpsr);
- __wfs(*__envp);
- feraiseexcept(__fpsr & FE_ALL_EXCEPT);
- return (0);
+static __inline int feupdateenv(const fenv_t* __envp) {
+ fexcept_t __fpscr;
+ fegetenv(&__fpscr);
+ fesetenv(__envp);
+ feraiseexcept(__fpscr & FE_ALL_EXCEPT);
+ return 0;
}
#if __BSD_VISIBLE
-static __inline int
-feenableexcept(int __mask)
-{
- fenv_t __old_fpsr, __new_fpsr;
-
- __rfs(&__old_fpsr);
- __new_fpsr = __old_fpsr | (__mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT;
- __wfs(__new_fpsr);
- return ((__old_fpsr >> _FPUSW_SHIFT) & FE_ALL_EXCEPT);
+static __inline int feenableexcept(int __mask) {
+ fenv_t __old_fpscr, __new_fpscr;
+ fegetenv(&__old_fpscr);
+ __new_fpscr = __old_fpscr | (__mask & FE_ALL_EXCEPT) << _FPSCR_ENABLE_SHIFT;
+ fesetenv(&__new_fpscr);
+ return ((__old_fpscr >> _FPSCR_ENABLE_SHIFT) & FE_ALL_EXCEPT);
}
-static __inline int
-fedisableexcept(int __mask)
-{
- fenv_t __old_fpsr, __new_fpsr;
-
- __rfs(&__old_fpsr);
- __new_fpsr = __old_fpsr & ~((__mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT);
- __wfs(__new_fpsr);
- return ((__old_fpsr >> _FPUSW_SHIFT) & FE_ALL_EXCEPT);
+static __inline int fedisableexcept(int __mask) {
+ fenv_t __old_fpscr, __new_fpscr;
+ fegetenv(&__old_fpscr);
+ __new_fpscr = __old_fpscr & ~((__mask & FE_ALL_EXCEPT) << _FPSCR_ENABLE_SHIFT);
+ fesetenv(&__new_fpscr);
+ return ((__old_fpscr >> _FPSCR_ENABLE_SHIFT) & FE_ALL_EXCEPT);
}
-static __inline int
-fegetexcept(void)
-{
- fenv_t __fpsr;
-
- __rfs(&__fpsr);
- return ((__fpsr & _ENABLE_MASK) >> _FPUSW_SHIFT);
+static __inline int fegetexcept(void) {
+ fenv_t __fpscr;
+ fegetenv(&__fpscr);
+ return ((__fpscr & _FPSCR_ENABLE_MASK) >> _FPSCR_ENABLE_SHIFT);
}
#endif /* __BSD_VISIBLE */
__END_DECLS
-#endif /* !_FENV_H_ */
+#endif /* !_FENV_H_ */