Merge "Correctly print RISC-V arch name on error when verifying ELF header."
diff --git a/README.md b/README.md
index 85c8190..8d8e583 100644
--- a/README.md
+++ b/README.md
@@ -246,6 +246,7 @@
### Debugging tips
1. Key error for a new codename in libc/libc.map.txt
+
e.g. what you add in libc/libc.map.txt is:
```
@@ -271,6 +272,7 @@
Solution: Ask in the team and wait for the update.
2. Use of undeclared identifier of the new system call in the test
+
Possible Solution: Check everything ready in the files mentioned above first.
Maybe glibc matters. Follow the example and try #if defined(__GLIBC__).
@@ -323,7 +325,7 @@
Note that we use our own custom gtest runner that offers a superset of the
options documented at
-<https://github.com/google/googletest/blob/master/googletest/docs/AdvancedGuide.md#running-test-programs-advanced-options>,
+<https://github.com/google/googletest/blob/main/docs/advanced.md#running-test-programs-advanced-options>,
in particular for test isolation and parallelism (both on by default).
### Device tests via CTS
diff --git a/TEST_MAPPING b/TEST_MAPPING
index 18e8bbc..f56e16a 100644
--- a/TEST_MAPPING
+++ b/TEST_MAPPING
@@ -83,5 +83,10 @@
{
"name": "toybox-tests"
}
+ ],
+ "kernel-presubmit": [
+ {
+ "name": "CtsBionicTestCases"
+ }
]
}
diff --git a/benchmarks/linker_relocation/include/linker_reloc_bench_asm.h b/benchmarks/linker_relocation/include/linker_reloc_bench_asm.h
index 2ff3d81..885e47f 100644
--- a/benchmarks/linker_relocation/include/linker_reloc_bench_asm.h
+++ b/benchmarks/linker_relocation/include/linker_reloc_bench_asm.h
@@ -42,6 +42,15 @@
#define DATA_WORD(val) .quad val
#define MAIN .globl main; main: mov w0, wzr; ret
+#elif defined(__riscv)
+
+// No `lga` in clang unless https://reviews.llvm.org/D107278 lands.
+// `la` is equivalent when using PIC (which we do) though.
+#define GOT_RELOC(sym) la a0, sym
+#define CALL(sym) call sym@plt
+#define DATA_WORD(val) .quad val
+#define MAIN .globl main; main: li a0, 0; ret
+
#elif defined(__i386__)
#define GOT_RELOC(sym) .long sym@got
diff --git a/libc/bionic/android_unsafe_frame_pointer_chase.cpp b/libc/bionic/android_unsafe_frame_pointer_chase.cpp
index a1cb3c6..1a59718 100644
--- a/libc/bionic/android_unsafe_frame_pointer_chase.cpp
+++ b/libc/bionic/android_unsafe_frame_pointer_chase.cpp
@@ -72,7 +72,13 @@
size_t num_frames = 0;
while (1) {
+#if defined(__riscv)
+ // Frame addresses seem to have been implemented incorrectly for RISC-V.
+ // See https://reviews.llvm.org/D87579.
+ auto* frame = reinterpret_cast<frame_record*>(begin - 16);
+#else
auto* frame = reinterpret_cast<frame_record*>(begin);
+#endif
if (num_frames < num_entries) {
buf[num_frames] = __bionic_clear_pac_bits(frame->return_addr);
}
diff --git a/libc/bionic/strtol.cpp b/libc/bionic/strtol.cpp
index ec72b09..05b4b53 100644
--- a/libc/bionic/strtol.cpp
+++ b/libc/bionic/strtol.cpp
@@ -208,9 +208,6 @@
return StrToI<long long, LLONG_MIN, LLONG_MAX, wchar_t>(s, end, base);
}
-// Public API since L, but not in any header.
-__strong_alias(strtoq, strtoll);
-
unsigned long strtoul(const char* s, char** end, int base) {
return StrToU<unsigned long, ULONG_MAX, char>(s, end, base);
}
@@ -234,6 +231,3 @@
uintmax_t wcstoumax(const wchar_t* s, wchar_t** end, int base) {
return StrToU<uintmax_t, UINTMAX_MAX, wchar_t>(s, end, base);
}
-
-// Public API since L, but not in any header.
-__strong_alias(strtouq, strtoull);
diff --git a/libc/include/regex.h b/libc/include/regex.h
index 156f9fd..be1418e 100644
--- a/libc/include/regex.h
+++ b/libc/include/regex.h
@@ -49,8 +49,8 @@
typedef struct {
int re_magic;
size_t re_nsub; /* number of parenthesized subexpressions */
- const char *re_endp; /* end pointer for REG_PEND */
- struct re_guts *re_g; /* none of your business :-) */
+ const char * _Null_unspecified re_endp; /* end pointer for REG_PEND */
+ struct re_guts * _Null_unspecified re_g; /* none of your business :-) */
} regex_t;
typedef struct {
@@ -99,10 +99,10 @@
#define REG_BACKR 02000 /* force use of backref code */
__BEGIN_DECLS
-int regcomp(regex_t* __re, const char* __regex, int __flags);
-size_t regerror(int __error_code, const regex_t* __re, char* __buf, size_t __n);
-int regexec(const regex_t* __re, const char* __s, size_t __match_count, regmatch_t __matches[], int __flags);
-void regfree(regex_t* __re);
+int regcomp(regex_t* _Nonnull __re, const char* _Nonnull __regex, int __flags);
+size_t regerror(int __error_code, const regex_t* _Nullable __re, char* _Nullable __buf, size_t __n);
+int regexec(const regex_t* _Nonnull __re, const char* _Nonnull __s, size_t __match_count, regmatch_t __matches[_Nullable], int __flags);
+void regfree(regex_t* _Nonnull __re);
__END_DECLS
#endif
diff --git a/libc/libc.map.txt b/libc/libc.map.txt
index dc1b6f6..5695dc6 100644
--- a/libc/libc.map.txt
+++ b/libc/libc.map.txt
@@ -1037,12 +1037,10 @@
strtold_l; # introduced=21
strtoll;
strtoll_l; # introduced=21
- strtoq; # introduced=21
strtoul;
strtoull;
strtoull_l; # introduced=21
strtoumax;
- strtouq; # introduced=21
strxfrm;
strxfrm_l; # introduced=21
swapoff; # introduced-arm=19 introduced-arm64=21 introduced-x86=19 introduced-x86_64=21
diff --git a/libc/malloc_debug/backtrace.cpp b/libc/malloc_debug/backtrace.cpp
index ab5c505..0649571 100644
--- a/libc/malloc_debug/backtrace.cpp
+++ b/libc/malloc_debug/backtrace.cpp
@@ -83,41 +83,24 @@
uintptr_t ip = _Unwind_GetIP(context);
- // The instruction pointer is pointing at the instruction after the return
- // call on all architectures.
- // Modify the pc to point at the real function.
- if (ip != 0) {
-#if defined(__arm__)
- // If the ip is suspiciously low, do nothing to avoid a segfault trying
- // to access this memory.
- if (ip >= 4096) {
- // Check bits [15:11] of the first halfword assuming the instruction
- // is 32 bits long. If the bits are any of these values, then our
- // assumption was correct:
- // b11101
- // b11110
- // b11111
- // Otherwise, this is a 16 bit instruction.
- uint16_t value = (*reinterpret_cast<uint16_t*>(ip - 2)) >> 11;
- if (value == 0x1f || value == 0x1e || value == 0x1d) {
- ip -= 4;
- } else {
- ip -= 2;
- }
- }
-#elif defined(__aarch64__)
- // All instructions are 4 bytes long, skip back one instruction.
- ip -= 4;
+ // `ip` is the address of the instruction *after* the call site in
+ // `context`, so we want to back up by one instruction. This is hard for
+ // every architecture except arm64, so we just make sure we're *inside*
+ // that instruction, not necessarily at the start of it. (If the value
+ // is too low to be valid, we just leave it alone.)
+ if (ip >= 4096) {
+#if defined(__aarch64__)
+ ip -= 4; // Exactly.
+#elif defined(__arm__) || defined(__riscv)
+ ip -= 2; // At least.
#elif defined(__i386__) || defined(__x86_64__)
- // It's difficult to decode exactly where the previous instruction is,
- // so subtract 1 to estimate where the instruction lives.
- ip--;
+ ip -= 1; // At least.
#endif
+ }
- // Do not record the frames that fall in our own shared library.
- if (g_current_code_map && (ip >= g_current_code_map->start) && ip < g_current_code_map->end) {
- return _URC_NO_REASON;
- }
+ // Do not record the frames that fall in our own shared library.
+ if (g_current_code_map && (ip >= g_current_code_map->start) && ip < g_current_code_map->end) {
+ return _URC_NO_REASON;
}
state->frames[state->cur_frame++] = ip;
diff --git a/tests/signal_test.cpp b/tests/signal_test.cpp
index 7f7f3db..fa648d2 100644
--- a/tests/signal_test.cpp
+++ b/tests/signal_test.cpp
@@ -823,9 +823,9 @@
#endif
TEST(signal, sigset_size) {
- // The setjmp implementations assume that sigset_t can fit in a
- // long. This is true because ARM and x86 have broken rt signal support,
- // and AArch64 and x86_64 both have a SIGRTMAX defined as 64.
+ // The setjmp implementations assume that sigset_t can fit in a long.
+ // This is true because the 32-bit ABIs have broken rt signal support,
+ // but the 64-bit ABIs both have a SIGRTMAX defined as 64.
#if defined(__BIONIC__)
static_assert(sizeof(sigset_t) <= sizeof(long), "sigset_t doesn't fit in a long");
#endif
diff --git a/tests/sys_ptrace_test.cpp b/tests/sys_ptrace_test.cpp
index a079ead..b8c1537 100644
--- a/tests/sys_ptrace_test.cpp
+++ b/tests/sys_ptrace_test.cpp
@@ -257,6 +257,9 @@
asm volatile("stm %0, { r0, r1, r2, r3 }" : : "r"(&data));
#elif defined(__aarch64__)
asm volatile("stp x0, x1, %0" : : "m"(data));
+#elif defined(__riscv)
+ UNUSED(data);
+ GTEST_LOG_(INFO) << "missing riscv64 instruction to store > 64 bits in one instruction";
#endif
}