diff --git a/libc/kernel/uapi/asm-riscv/asm/auxvec.h b/libc/kernel/uapi/asm-riscv/asm/auxvec.h
index c70be17..30c8bec 100644
--- a/libc/kernel/uapi/asm-riscv/asm/auxvec.h
+++ b/libc/kernel/uapi/asm-riscv/asm/auxvec.h
@@ -28,4 +28,5 @@
 #define AT_L3_CACHESIZE 46
 #define AT_L3_CACHEGEOMETRY 47
 #define AT_VECTOR_SIZE_ARCH 9
+#define AT_MINSIGSTKSZ 51
 #endif
diff --git a/libc/kernel/uapi/asm-riscv/asm/hwcap.h b/libc/kernel/uapi/asm-riscv/asm/hwcap.h
index d130cf7..e22e14a 100644
--- a/libc/kernel/uapi/asm-riscv/asm/hwcap.h
+++ b/libc/kernel/uapi/asm-riscv/asm/hwcap.h
@@ -24,4 +24,5 @@
 #define COMPAT_HWCAP_ISA_F (1 << ('F' - 'A'))
 #define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A'))
 #define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A'))
+#define COMPAT_HWCAP_ISA_V (1 << ('V' - 'A'))
 #endif
diff --git a/libc/kernel/uapi/asm-riscv/asm/hwprobe.h b/libc/kernel/uapi/asm-riscv/asm/hwprobe.h
index 0722805..04c9213 100644
--- a/libc/kernel/uapi/asm-riscv/asm/hwprobe.h
+++ b/libc/kernel/uapi/asm-riscv/asm/hwprobe.h
@@ -31,6 +31,10 @@
 #define RISCV_HWPROBE_KEY_IMA_EXT_0 4
 #define RISCV_HWPROBE_IMA_FD (1 << 0)
 #define RISCV_HWPROBE_IMA_C (1 << 1)
+#define RISCV_HWPROBE_IMA_V (1 << 2)
+#define RISCV_HWPROBE_EXT_ZBA (1 << 3)
+#define RISCV_HWPROBE_EXT_ZBB (1 << 4)
+#define RISCV_HWPROBE_EXT_ZBS (1 << 5)
 #define RISCV_HWPROBE_KEY_CPUPERF_0 5
 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
 #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
diff --git a/libc/kernel/uapi/asm-riscv/asm/kvm.h b/libc/kernel/uapi/asm-riscv/asm/kvm.h
index bc7baef..c595872 100644
--- a/libc/kernel/uapi/asm-riscv/asm/kvm.h
+++ b/libc/kernel/uapi/asm-riscv/asm/kvm.h
@@ -22,6 +22,7 @@
 #include <linux/types.h>
 #include <asm/bitsperlong.h>
 #include <asm/ptrace.h>
+#define __KVM_HAVE_IRQ_LINE
 #define __KVM_HAVE_READONLY_MEM
 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
 #define KVM_INTERRUPT_SET - 1U
@@ -95,6 +96,8 @@
   KVM_RISCV_ISA_EXT_ZICBOZ,
   KVM_RISCV_ISA_EXT_ZBB,
   KVM_RISCV_ISA_EXT_SSAIA,
+  KVM_RISCV_ISA_EXT_V,
+  KVM_RISCV_ISA_EXT_SVNAPOT,
   KVM_RISCV_ISA_EXT_MAX,
 };
 enum KVM_RISCV_SBI_EXT_ID {
@@ -139,5 +142,46 @@
 #define KVM_REG_RISCV_SBI_MULTI_REG(__ext_id) ((__ext_id) / __BITS_PER_LONG)
 #define KVM_REG_RISCV_SBI_MULTI_MASK(__ext_id) (1UL << ((__ext_id) % __BITS_PER_LONG))
 #define KVM_REG_RISCV_SBI_MULTI_REG_LAST KVM_REG_RISCV_SBI_MULTI_REG(KVM_RISCV_SBI_EXT_MAX - 1)
+#define KVM_REG_RISCV_VECTOR (0x09 << KVM_REG_RISCV_TYPE_SHIFT)
+#define KVM_REG_RISCV_VECTOR_CSR_REG(name) (offsetof(struct __riscv_v_ext_state, name) / sizeof(unsigned long))
+#define KVM_REG_RISCV_VECTOR_REG(n) ((n) + sizeof(struct __riscv_v_ext_state) / sizeof(unsigned long))
+#define KVM_DEV_RISCV_APLIC_ALIGN 0x1000
+#define KVM_DEV_RISCV_APLIC_SIZE 0x4000
+#define KVM_DEV_RISCV_APLIC_MAX_HARTS 0x4000
+#define KVM_DEV_RISCV_IMSIC_ALIGN 0x1000
+#define KVM_DEV_RISCV_IMSIC_SIZE 0x1000
+#define KVM_DEV_RISCV_AIA_GRP_CONFIG 0
+#define KVM_DEV_RISCV_AIA_CONFIG_MODE 0
+#define KVM_DEV_RISCV_AIA_CONFIG_IDS 1
+#define KVM_DEV_RISCV_AIA_CONFIG_SRCS 2
+#define KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS 3
+#define KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT 4
+#define KVM_DEV_RISCV_AIA_CONFIG_HART_BITS 5
+#define KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS 6
+#define KVM_DEV_RISCV_AIA_MODE_EMUL 0
+#define KVM_DEV_RISCV_AIA_MODE_HWACCEL 1
+#define KVM_DEV_RISCV_AIA_MODE_AUTO 2
+#define KVM_DEV_RISCV_AIA_IDS_MIN 63
+#define KVM_DEV_RISCV_AIA_IDS_MAX 2048
+#define KVM_DEV_RISCV_AIA_SRCS_MAX 1024
+#define KVM_DEV_RISCV_AIA_GROUP_BITS_MAX 8
+#define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MIN 24
+#define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MAX 56
+#define KVM_DEV_RISCV_AIA_HART_BITS_MAX 16
+#define KVM_DEV_RISCV_AIA_GUEST_BITS_MAX 8
+#define KVM_DEV_RISCV_AIA_GRP_ADDR 1
+#define KVM_DEV_RISCV_AIA_ADDR_APLIC 0
+#define KVM_DEV_RISCV_AIA_ADDR_IMSIC(__vcpu) (1 + (__vcpu))
+#define KVM_DEV_RISCV_AIA_ADDR_MAX (1 + KVM_DEV_RISCV_APLIC_MAX_HARTS)
+#define KVM_DEV_RISCV_AIA_GRP_CTRL 2
+#define KVM_DEV_RISCV_AIA_CTRL_INIT 0
+#define KVM_DEV_RISCV_AIA_GRP_APLIC 3
+#define KVM_DEV_RISCV_AIA_GRP_IMSIC 4
+#define KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS 12
+#define KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK ((1U << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) - 1)
+#define KVM_DEV_RISCV_AIA_IMSIC_MKATTR(__vcpu,__isel) (((__vcpu) << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) | ((__isel) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK))
+#define KVM_DEV_RISCV_AIA_IMSIC_GET_ISEL(__attr) ((__attr) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK)
+#define KVM_DEV_RISCV_AIA_IMSIC_GET_VCPU(__attr) ((__attr) >> KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS)
+#define KVM_NR_IRQCHIPS 1
 #endif
 #endif
diff --git a/libc/kernel/uapi/asm-riscv/asm/ptrace.h b/libc/kernel/uapi/asm-riscv/asm/ptrace.h
index 94e4ac9..f491908 100644
--- a/libc/kernel/uapi/asm-riscv/asm/ptrace.h
+++ b/libc/kernel/uapi/asm-riscv/asm/ptrace.h
@@ -67,10 +67,28 @@
   __u32 fcsr;
   __u32 reserved[3];
 };
+struct __riscv_ctx_hdr {
+  __u32 magic;
+  __u32 size;
+};
+struct __riscv_extra_ext_header {
+  __u32 __padding[129] __attribute__((aligned(16)));
+  __u32 reserved;
+  struct __riscv_ctx_hdr hdr;
+};
 union __riscv_fp_state {
   struct __riscv_f_ext_state f;
   struct __riscv_d_ext_state d;
   struct __riscv_q_ext_state q;
 };
+struct __riscv_v_ext_state {
+  unsigned long vstart;
+  unsigned long vl;
+  unsigned long vtype;
+  unsigned long vcsr;
+  unsigned long vlenb;
+  void * datap;
+};
+#define RISCV_MAX_VLENB (8192)
 #endif
 #endif
diff --git a/libc/kernel/uapi/asm-riscv/asm/sigcontext.h b/libc/kernel/uapi/asm-riscv/asm/sigcontext.h
index 0553b94..bf00435 100644
--- a/libc/kernel/uapi/asm-riscv/asm/sigcontext.h
+++ b/libc/kernel/uapi/asm-riscv/asm/sigcontext.h
@@ -19,8 +19,19 @@
 #ifndef _UAPI_ASM_RISCV_SIGCONTEXT_H
 #define _UAPI_ASM_RISCV_SIGCONTEXT_H
 #include <asm/ptrace.h>
+#define RISCV_V_MAGIC 0x53465457
+#define END_MAGIC 0x0
+#define END_HDR_SIZE 0x0
+#ifndef __ASSEMBLY__
+struct __sc_riscv_v_state {
+  struct __riscv_v_ext_state v_state;
+} __attribute__((aligned(16)));
 struct sigcontext {
   struct user_regs_struct sc_regs;
-  union __riscv_fp_state sc_fpregs;
+  union {
+    union __riscv_fp_state sc_fpregs;
+    struct __riscv_extra_ext_header sc_extdesc;
+  };
 };
 #endif
+#endif