commit 76a1d45599fb287742bfe645dea117039fca7949
author Christopher Ferris <cferris@google.com> Wed Jun 27 14:12:29 2018 -0700
committer Christopher Ferris <cferris@google.com> Wed Jun 27 14:12:29 2018 -0700
tree ea764b786629b81444fb42469cfdbb100ef29112
parent 6747bd1631c24f76684278020056ee0d41cbb402

Update to v4.17.3 kernel headers.

Test: Builds, boots on a walleye.
Change-Id: I389d8b61ec00ea309e38d1b1a2e0dace48c21edb

libc/kernel/uapi/rdma/mlx4-abi.h

diff --git a/libc/kernel/uapi/rdma/mlx4-abi.h b/libc/kernel/uapi/rdma/mlx4-abi.h
index 078b386..121762b 100644
--- a/libc/kernel/uapi/rdma/mlx4-abi.h
+++ b/libc/kernel/uapi/rdma/mlx4-abi.h
@@ -26,6 +26,9 @@
   __u16 bf_reg_size;
   __u16 bf_regs_per_page;
 };
+enum {
+  MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0,
+};
 struct mlx4_ib_alloc_ucontext_resp {
   __u32 dev_caps;
   __u32 qp_tab_size;
@@ -38,26 +41,26 @@
   __u32 reserved;
 };
 struct mlx4_ib_create_cq {
-  __u64 buf_addr;
-  __u64 db_addr;
+  __aligned_u64 buf_addr;
+  __aligned_u64 db_addr;
 };
 struct mlx4_ib_create_cq_resp {
   __u32 cqn;
   __u32 reserved;
 };
 struct mlx4_ib_resize_cq {
-  __u64 buf_addr;
+  __aligned_u64 buf_addr;
 };
 struct mlx4_ib_create_srq {
-  __u64 buf_addr;
-  __u64 db_addr;
+  __aligned_u64 buf_addr;
+  __aligned_u64 db_addr;
 };
 struct mlx4_ib_create_srq_resp {
   __u32 srqn;
   __u32 reserved;
 };
 struct mlx4_ib_create_qp_rss {
-  __u64 rx_hash_fields_mask;
+  __aligned_u64 rx_hash_fields_mask;
   __u8 rx_hash_function;
   __u8 reserved[7];
   __u8 rx_hash_key[40];
@@ -65,8 +68,8 @@
   __u32 reserved1;
 };
 struct mlx4_ib_create_qp {
-  __u64 buf_addr;
-  __u64 db_addr;
+  __aligned_u64 buf_addr;
+  __aligned_u64 db_addr;
   __u8 log_sq_bb_count;
   __u8 log_sq_stride;
   __u8 sq_no_prefetch;
@@ -74,8 +77,8 @@
   __u32 inl_recv_sz;
 };
 struct mlx4_ib_create_wq {
-  __u64 buf_addr;
-  __u64 db_addr;
+  __aligned_u64 buf_addr;
+  __aligned_u64 db_addr;
   __u8 log_range_size;
   __u8 reserved[3];
   __u32 comp_mask;
@@ -99,6 +102,28 @@
   MLX4_IB_RX_HASH_SRC_PORT_TCP = 1 << 4,
   MLX4_IB_RX_HASH_DST_PORT_TCP = 1 << 5,
   MLX4_IB_RX_HASH_SRC_PORT_UDP = 1 << 6,
-  MLX4_IB_RX_HASH_DST_PORT_UDP = 1 << 7
+  MLX4_IB_RX_HASH_DST_PORT_UDP = 1 << 7,
+  MLX4_IB_RX_HASH_INNER = 1ULL << 31,
+};
+struct mlx4_ib_rss_caps {
+  __aligned_u64 rx_hash_fields_mask;
+  __u8 rx_hash_function;
+  __u8 reserved[7];
+};
+enum query_device_resp_mask {
+  MLX4_IB_QUERY_DEV_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
+};
+struct mlx4_ib_tso_caps {
+  __u32 max_tso;
+  __u32 supported_qpts;
+};
+struct mlx4_uverbs_ex_query_device_resp {
+  __u32 comp_mask;
+  __u32 response_length;
+  __aligned_u64 hca_core_clock_offset;
+  __u32 max_inl_recv_sz;
+  __u32 reserved;
+  struct mlx4_ib_rss_caps rss_caps;
+  struct mlx4_ib_tso_caps tso_caps;
 };
 #endif