Update to v4.17.3 kernel headers.
Test: Builds, boots on a walleye.
Change-Id: I389d8b61ec00ea309e38d1b1a2e0dace48c21edb
diff --git a/libc/kernel/uapi/linux/pci_regs.h b/libc/kernel/uapi/linux/pci_regs.h
index 148f2b4..4ef3837 100644
--- a/libc/kernel/uapi/linux/pci_regs.h
+++ b/libc/kernel/uapi/linux/pci_regs.h
@@ -430,6 +430,7 @@
#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001
#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002
#define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003
+#define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004
#define PCI_EXP_LNKCAP_MLW 0x000003f0
#define PCI_EXP_LNKCAP_ASPMS 0x00000c00
#define PCI_EXP_LNKCAP_L0SEL 0x00007000
@@ -457,6 +458,7 @@
#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001
#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002
#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003
+#define PCI_EXP_LNKSTA_CLS_16_0GB 0x0004
#define PCI_EXP_LNKSTA_NLW 0x03f0
#define PCI_EXP_LNKSTA_NLW_X1 0x0010
#define PCI_EXP_LNKSTA_NLW_X2 0x0020
@@ -524,15 +526,19 @@
#define PCI_EXP_RTSTA_PME 0x00010000
#define PCI_EXP_RTSTA_PENDING 0x00020000
#define PCI_EXP_DEVCAP2 36
+#define PCI_EXP_DEVCAP2_COMP_TMOUT_DIS 0x00000010
#define PCI_EXP_DEVCAP2_ARI 0x00000020
#define PCI_EXP_DEVCAP2_ATOMIC_ROUTE 0x00000040
+#define PCI_EXP_DEVCAP2_ATOMIC_COMP32 0x00000080
#define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100
+#define PCI_EXP_DEVCAP2_ATOMIC_COMP128 0x00000200
#define PCI_EXP_DEVCAP2_LTR 0x00000800
#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000
#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000
#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000
#define PCI_EXP_DEVCTL2 40
#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f
+#define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS 0x0010
#define PCI_EXP_DEVCTL2_ARI 0x0020
#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040
#define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080
@@ -548,6 +554,7 @@
#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002
#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004
#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008
+#define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010
#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100
#define PCI_EXP_LNKCTL2 48
#define PCI_EXP_LNKSTA2 50
@@ -819,19 +826,21 @@
#define PCI_TPH_CAP_ST_SHIFT 16
#define PCI_TPH_BASE_SIZEOF 12
#define PCI_EXP_DPC_CAP 4
-#define PCI_EXP_DPC_IRQ 0x1f
-#define PCI_EXP_DPC_CAP_RP_EXT 0x20
-#define PCI_EXP_DPC_CAP_POISONED_TLP 0x40
-#define PCI_EXP_DPC_CAP_SW_TRIGGER 0x80
-#define PCI_EXP_DPC_RP_PIO_LOG_SIZE 0xF00
+#define PCI_EXP_DPC_IRQ 0x001F
+#define PCI_EXP_DPC_CAP_RP_EXT 0x0020
+#define PCI_EXP_DPC_CAP_POISONED_TLP 0x0040
+#define PCI_EXP_DPC_CAP_SW_TRIGGER 0x0080
+#define PCI_EXP_DPC_RP_PIO_LOG_SIZE 0x0F00
#define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000
#define PCI_EXP_DPC_CTL 6
-#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x02
-#define PCI_EXP_DPC_CTL_INT_EN 0x08
+#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x0002
+#define PCI_EXP_DPC_CTL_INT_EN 0x0008
#define PCI_EXP_DPC_STATUS 8
-#define PCI_EXP_DPC_STATUS_TRIGGER 0x01
-#define PCI_EXP_DPC_STATUS_INTERRUPT 0x08
-#define PCI_EXP_DPC_RP_BUSY 0x10
+#define PCI_EXP_DPC_STATUS_TRIGGER 0x0001
+#define PCI_EXP_DPC_STATUS_TRIGGER_RSN 0x0006
+#define PCI_EXP_DPC_STATUS_INTERRUPT 0x0008
+#define PCI_EXP_DPC_RP_BUSY 0x0010
+#define PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT 0x0060
#define PCI_EXP_DPC_SOURCE_ID 10
#define PCI_EXP_DPC_RP_PIO_STATUS 0x0C
#define PCI_EXP_DPC_RP_PIO_MASK 0x10