| commit | 73840b56b2590fc8c93768d7d3d70122b4caa6b3 | [log] [tgz] |
|---|---|---|
| author | Elliott Hughes <enh@google.com> | Tue Nov 15 17:22:35 2022 +0000 |
| committer | Gerrit Code Review <noreply-gerritcodereview@google.com> | Tue Nov 15 17:22:35 2022 +0000 |
| tree | d46fc7e6f6da54d84e162249933c8be96b4dbbfd | |
| parent | 56c4db9aeb0016867647974bf6d2661e6ec14747 [diff] | |
| parent | 89719df10778e0f8405ce5904d936517b0b4116c [diff] |
Merge "Update sys_ptrace_test.cpp for riscv64."
diff --git a/tests/sys_ptrace_test.cpp b/tests/sys_ptrace_test.cpp index a079ead..b8c1537 100644 --- a/tests/sys_ptrace_test.cpp +++ b/tests/sys_ptrace_test.cpp
@@ -257,6 +257,9 @@ asm volatile("stm %0, { r0, r1, r2, r3 }" : : "r"(&data)); #elif defined(__aarch64__) asm volatile("stp x0, x1, %0" : : "m"(data)); +#elif defined(__riscv) + UNUSED(data); + GTEST_LOG_(INFO) << "missing riscv64 instruction to store > 64 bits in one instruction"; #endif }