commit 67d1e5eb749124a14d6b5ecde63b2a4604830f3b
author Christopher Ferris <cferris@google.com> Tue Oct 31 13:36:37 2023 -0700
committer Christopher Ferris <cferris@google.com> Tue Oct 31 13:36:37 2023 -0700
tree f3df775a7ac267aa585b7ffcbbaea6853f976208
parent d0f5e4cf8aad28941695b0077266ed8bf1d9cc7c

Update to v6.6 kernel headers.

Kernel headers coming from:

Git: https://android.googlesource.com/kernel/common/
Branch: android-mainline
Tag: android-mainline-6.6

Test: Builds and bionic unit tests pass on raven.
Test: Able to log in to an Android GO 32 bit device.
Change-Id: Ib5ff5a23f382721d98d1e428a295c6794b190d8d

libc/kernel/uapi/rdma/bnxt_re-abi.h

diff --git a/libc/kernel/uapi/rdma/bnxt_re-abi.h b/libc/kernel/uapi/rdma/bnxt_re-abi.h
index 68cb06a..8324923 100644
--- a/libc/kernel/uapi/rdma/bnxt_re-abi.h
+++ b/libc/kernel/uapi/rdma/bnxt_re-abi.h
@@ -28,6 +28,7 @@
   BNXT_RE_UCNTX_CMASK_HAVE_CCTX = 0x1ULL,
   BNXT_RE_UCNTX_CMASK_HAVE_MODE = 0x02ULL,
   BNXT_RE_UCNTX_CMASK_WC_DPI_ENABLED = 0x04ULL,
+  BNXT_RE_UCNTX_CMASK_DBR_PACING_ENABLED = 0x08ULL,
 };
 enum bnxt_re_wqe_mode {
   BNXT_QPLIB_WQE_MODE_STATIC = 0x00,
@@ -89,9 +90,12 @@
 };
 enum bnxt_re_objects {
   BNXT_RE_OBJECT_ALLOC_PAGE = (1U << UVERBS_ID_NS_SHIFT),
+  BNXT_RE_OBJECT_NOTIFY_DRV,
 };
 enum bnxt_re_alloc_page_type {
   BNXT_RE_ALLOC_WC_PAGE = 0,
+  BNXT_RE_ALLOC_DBR_BAR_PAGE,
+  BNXT_RE_ALLOC_DBR_PAGE,
 };
 enum bnxt_re_var_alloc_page_attrs {
   BNXT_RE_ALLOC_PAGE_HANDLE = (1U << UVERBS_ID_NS_SHIFT),
@@ -107,4 +111,7 @@
   BNXT_RE_METHOD_ALLOC_PAGE = (1U << UVERBS_ID_NS_SHIFT),
   BNXT_RE_METHOD_DESTROY_PAGE,
 };
+enum bnxt_re_notify_drv_methods {
+  BNXT_RE_METHOD_NOTIFY_DRV = (1U << UVERBS_ID_NS_SHIFT),
+};
 #endif

libc/kernel/uapi/rdma/irdma-abi.h

diff --git a/libc/kernel/uapi/rdma/irdma-abi.h b/libc/kernel/uapi/rdma/irdma-abi.h
index b6840cf..b2eb258 100644
--- a/libc/kernel/uapi/rdma/irdma-abi.h
+++ b/libc/kernel/uapi/rdma/irdma-abi.h
@@ -25,10 +25,15 @@
   IRDMA_MEMREG_TYPE_QP = 1,
   IRDMA_MEMREG_TYPE_CQ = 2,
 };
+enum {
+  IRDMA_ALLOC_UCTX_USE_RAW_ATTR = 1 << 0,
+  IRDMA_ALLOC_UCTX_MIN_HW_WQ_SIZE = 1 << 1,
+};
 struct irdma_alloc_ucontext_req {
   __u32 rsvd32;
   __u8 userspace_ver;
   __u8 rsvd8[3];
+  __aligned_u64 comp_mask;
 };
 struct irdma_alloc_ucontext_resp {
   __u32 max_pds;
@@ -48,6 +53,9 @@
   __u16 max_hw_sq_chunk;
   __u8 hw_rev;
   __u8 rsvd2;
+  __aligned_u64 comp_mask;
+  __u16 min_hw_wq_size;
+  __u8 rsvd3[6];
 };
 struct irdma_alloc_pd_resp {
   __u32 pd_id;