diff --git a/libc/kernel/uapi/drm/amdgpu_drm.h b/libc/kernel/uapi/drm/amdgpu_drm.h
index d4ae7d4..19d96bc 100644
--- a/libc/kernel/uapi/drm/amdgpu_drm.h
+++ b/libc/kernel/uapi/drm/amdgpu_drm.h
@@ -60,7 +60,8 @@
 #define AMDGPU_GEM_DOMAIN_GDS 0x8
 #define AMDGPU_GEM_DOMAIN_GWS 0x10
 #define AMDGPU_GEM_DOMAIN_OA 0x20
-#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)
+#define AMDGPU_GEM_DOMAIN_DOORBELL 0x40
+#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA | AMDGPU_GEM_DOMAIN_DOORBELL)
 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
diff --git a/libc/kernel/uapi/drm/drm.h b/libc/kernel/uapi/drm/drm.h
index 1954452..8eedf28 100644
--- a/libc/kernel/uapi/drm/drm.h
+++ b/libc/kernel/uapi/drm/drm.h
@@ -430,6 +430,13 @@
   __u32 first_signaled;
   __u32 pad;
 };
+struct drm_syncobj_eventfd {
+  __u32 handle;
+  __u32 flags;
+  __u64 point;
+  __s32 fd;
+  __u32 pad;
+};
 struct drm_syncobj_array {
   __u64 handles;
   __u32 count_handles;
@@ -574,6 +581,7 @@
 #define DRM_IOCTL_SYNCOBJ_TRANSFER DRM_IOWR(0xCC, struct drm_syncobj_transfer)
 #define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL DRM_IOWR(0xCD, struct drm_syncobj_timeline_array)
 #define DRM_IOCTL_MODE_GETFB2 DRM_IOWR(0xCE, struct drm_mode_fb_cmd2)
+#define DRM_IOCTL_SYNCOBJ_EVENTFD DRM_IOWR(0xCF, struct drm_syncobj_eventfd)
 #define DRM_COMMAND_BASE 0x40
 #define DRM_COMMAND_END 0xA0
 struct drm_event {
diff --git a/libc/kernel/uapi/drm/i915_drm.h b/libc/kernel/uapi/drm/i915_drm.h
index ae79ab3..c2b1c18 100644
--- a/libc/kernel/uapi/drm/i915_drm.h
+++ b/libc/kernel/uapi/drm/i915_drm.h
@@ -59,10 +59,10 @@
 #define I915_PMU_SAMPLE_MASK (0xf)
 #define I915_PMU_SAMPLE_INSTANCE_BITS (8)
 #define I915_PMU_CLASS_SHIFT (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS)
-#define __I915_PMU_ENGINE(class,instance,sample) ((class) << I915_PMU_CLASS_SHIFT | (instance) << I915_PMU_SAMPLE_BITS | (sample))
-#define I915_PMU_ENGINE_BUSY(class,instance) __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY)
-#define I915_PMU_ENGINE_WAIT(class,instance) __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT)
-#define I915_PMU_ENGINE_SEMA(class,instance) __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
+#define __I915_PMU_ENGINE(__linux_class,instance,sample) ((__linux_class) << I915_PMU_CLASS_SHIFT | (instance) << I915_PMU_SAMPLE_BITS | (sample))
+#define I915_PMU_ENGINE_BUSY(__linux_class,instance) __I915_PMU_ENGINE(__linux_class, instance, I915_SAMPLE_BUSY)
+#define I915_PMU_ENGINE_WAIT(__linux_class,instance) __I915_PMU_ENGINE(__linux_class, instance, I915_SAMPLE_WAIT)
+#define I915_PMU_ENGINE_SEMA(__linux_class,instance) __I915_PMU_ENGINE(__linux_class, instance, I915_SAMPLE_SEMA)
 #define __I915_PMU_GT_SHIFT (60)
 #define ___I915_PMU_OTHER(gt,x) (((__u64) __I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) | ((__u64) (gt) << __I915_PMU_GT_SHIFT))
 #define __I915_PMU_OTHER(x) ___I915_PMU_OTHER(0, x)
diff --git a/libc/kernel/uapi/drm/ivpu_accel.h b/libc/kernel/uapi/drm/ivpu_accel.h
index e148a5b..5d9edbd 100644
--- a/libc/kernel/uapi/drm/ivpu_accel.h
+++ b/libc/kernel/uapi/drm/ivpu_accel.h
@@ -49,23 +49,28 @@
 #define DRM_IVPU_PARAM_UNIQUE_INFERENCE_ID 10
 #define DRM_IVPU_PARAM_TILE_CONFIG 11
 #define DRM_IVPU_PARAM_SKU 12
+#define DRM_IVPU_PARAM_CAPABILITIES 13
 #define DRM_IVPU_PLATFORM_TYPE_SILICON 0
 #define DRM_IVPU_CONTEXT_PRIORITY_IDLE 0
 #define DRM_IVPU_CONTEXT_PRIORITY_NORMAL 1
 #define DRM_IVPU_CONTEXT_PRIORITY_FOCUS 2
 #define DRM_IVPU_CONTEXT_PRIORITY_REALTIME 3
+#define DRM_IVPU_CAP_METRIC_STREAMER 1
+#define DRM_IVPU_CAP_DMA_MEMORY_RANGE 2
 struct drm_ivpu_param {
   __u32 param;
   __u32 index;
   __u64 value;
 };
-#define DRM_IVPU_BO_HIGH_MEM 0x00000001
+#define DRM_IVPU_BO_SHAVE_MEM 0x00000001
+#define DRM_IVPU_BO_HIGH_MEM DRM_IVPU_BO_SHAVE_MEM
 #define DRM_IVPU_BO_MAPPABLE 0x00000002
+#define DRM_IVPU_BO_DMA_MEM 0x00000004
 #define DRM_IVPU_BO_CACHED 0x00000000
 #define DRM_IVPU_BO_UNCACHED 0x00010000
 #define DRM_IVPU_BO_WC 0x00020000
 #define DRM_IVPU_BO_CACHE_MASK 0x00030000
-#define DRM_IVPU_BO_FLAGS (DRM_IVPU_BO_HIGH_MEM | DRM_IVPU_BO_MAPPABLE | DRM_IVPU_BO_CACHE_MASK)
+#define DRM_IVPU_BO_FLAGS (DRM_IVPU_BO_HIGH_MEM | DRM_IVPU_BO_MAPPABLE | DRM_IVPU_BO_DMA_MEM | DRM_IVPU_BO_CACHE_MASK)
 struct drm_ivpu_bo_create {
   __u64 size;
   __u32 flags;
diff --git a/libc/kernel/uapi/drm/nouveau_drm.h b/libc/kernel/uapi/drm/nouveau_drm.h
index 150f729..2c38494 100644
--- a/libc/kernel/uapi/drm/nouveau_drm.h
+++ b/libc/kernel/uapi/drm/nouveau_drm.h
@@ -23,11 +23,43 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
+#define NOUVEAU_GETPARAM_PCI_VENDOR 3
+#define NOUVEAU_GETPARAM_PCI_DEVICE 4
+#define NOUVEAU_GETPARAM_BUS_TYPE 5
+#define NOUVEAU_GETPARAM_FB_SIZE 8
+#define NOUVEAU_GETPARAM_AGP_SIZE 9
+#define NOUVEAU_GETPARAM_CHIPSET_ID 11
+#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
+#define NOUVEAU_GETPARAM_GRAPH_UNITS 13
+#define NOUVEAU_GETPARAM_PTIMER_TIME 14
+#define NOUVEAU_GETPARAM_HAS_BO_USAGE 15
+#define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16
+#define NOUVEAU_GETPARAM_EXEC_PUSH_MAX 17
+struct drm_nouveau_getparam {
+  __u64 param;
+  __u64 value;
+};
+struct drm_nouveau_channel_alloc {
+  __u32 fb_ctxdma_handle;
+  __u32 tt_ctxdma_handle;
+  __s32 channel;
+  __u32 pushbuf_domains;
+  __u32 notifier_handle;
+  struct {
+    __u32 handle;
+    __u32 grclass;
+  } subchan[8];
+  __u32 nr_subchan;
+};
+struct drm_nouveau_channel_free {
+  __s32 channel;
+};
 #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
 #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
 #define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
 #define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
 #define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4)
+#define NOUVEAU_GEM_DOMAIN_NO_SHARE (1 << 5)
 #define NOUVEAU_GEM_TILE_COMP 0x00030000
 #define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
 #define NOUVEAU_GEM_TILE_16BPP 0x00000001
@@ -81,6 +113,7 @@
   __u32 pad;
   __u64 offset;
   __u64 length;
+#define NOUVEAU_GEM_PUSHBUF_NO_PREFETCH (1 << 23)
 };
 struct drm_nouveau_gem_pushbuf {
   __u32 channel;
@@ -105,6 +138,55 @@
 struct drm_nouveau_gem_cpu_fini {
   __u32 handle;
 };
+struct drm_nouveau_sync {
+  __u32 flags;
+#define DRM_NOUVEAU_SYNC_SYNCOBJ 0x0
+#define DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ 0x1
+#define DRM_NOUVEAU_SYNC_TYPE_MASK 0xf
+  __u32 handle;
+  __u64 timeline_value;
+};
+struct drm_nouveau_vm_init {
+  __u64 kernel_managed_addr;
+  __u64 kernel_managed_size;
+};
+struct drm_nouveau_vm_bind_op {
+  __u32 op;
+#define DRM_NOUVEAU_VM_BIND_OP_MAP 0x0
+#define DRM_NOUVEAU_VM_BIND_OP_UNMAP 0x1
+  __u32 flags;
+#define DRM_NOUVEAU_VM_BIND_SPARSE (1 << 8)
+  __u32 handle;
+  __u32 pad;
+  __u64 addr;
+  __u64 bo_offset;
+  __u64 range;
+};
+struct drm_nouveau_vm_bind {
+  __u32 op_count;
+  __u32 flags;
+#define DRM_NOUVEAU_VM_BIND_RUN_ASYNC 0x1
+  __u32 wait_count;
+  __u32 sig_count;
+  __u64 wait_ptr;
+  __u64 sig_ptr;
+  __u64 op_ptr;
+};
+struct drm_nouveau_exec_push {
+  __u64 va;
+  __u32 va_len;
+  __u32 flags;
+#define DRM_NOUVEAU_EXEC_PUSH_NO_PREFETCH 0x1
+};
+struct drm_nouveau_exec {
+  __u32 channel;
+  __u32 push_count;
+  __u32 wait_count;
+  __u32 sig_count;
+  __u64 wait_ptr;
+  __u64 sig_ptr;
+  __u64 push_ptr;
+};
 #define DRM_NOUVEAU_GETPARAM 0x00
 #define DRM_NOUVEAU_SETPARAM 0x01
 #define DRM_NOUVEAU_CHANNEL_ALLOC 0x02
@@ -115,6 +197,9 @@
 #define DRM_NOUVEAU_NVIF 0x07
 #define DRM_NOUVEAU_SVM_INIT 0x08
 #define DRM_NOUVEAU_SVM_BIND 0x09
+#define DRM_NOUVEAU_VM_INIT 0x10
+#define DRM_NOUVEAU_VM_BIND 0x11
+#define DRM_NOUVEAU_EXEC 0x12
 #define DRM_NOUVEAU_GEM_NEW 0x40
 #define DRM_NOUVEAU_GEM_PUSHBUF 0x41
 #define DRM_NOUVEAU_GEM_CPU_PREP 0x42
@@ -147,6 +232,9 @@
 #define NOUVEAU_SVM_BIND_VALID_MASK ((1ULL << NOUVEAU_SVM_BIND_VALID_BITS) - 1)
 #define NOUVEAU_SVM_BIND_COMMAND__MIGRATE 0
 #define NOUVEAU_SVM_BIND_TARGET__GPU_VRAM (1UL << 31)
+#define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
+#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
+#define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
 #define DRM_IOCTL_NOUVEAU_SVM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_INIT, struct drm_nouveau_svm_init)
 #define DRM_IOCTL_NOUVEAU_SVM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_BIND, struct drm_nouveau_svm_bind)
 #define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
@@ -154,6 +242,9 @@
 #define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
 #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
 #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
+#define DRM_IOCTL_NOUVEAU_VM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_INIT, struct drm_nouveau_vm_init)
+#define DRM_IOCTL_NOUVEAU_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_BIND, struct drm_nouveau_vm_bind)
+#define DRM_IOCTL_NOUVEAU_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_EXEC, struct drm_nouveau_exec)
 #ifdef __cplusplus
 }
 #endif
diff --git a/libc/kernel/uapi/drm/virtgpu_drm.h b/libc/kernel/uapi/drm/virtgpu_drm.h
index 342282d..cf73121 100644
--- a/libc/kernel/uapi/drm/virtgpu_drm.h
+++ b/libc/kernel/uapi/drm/virtgpu_drm.h
@@ -42,6 +42,13 @@
   __u32 handle;
   __u32 pad;
 };
+#define VIRTGPU_EXECBUF_SYNCOBJ_RESET 0x01
+#define VIRTGPU_EXECBUF_SYNCOBJ_FLAGS (VIRTGPU_EXECBUF_SYNCOBJ_RESET | 0)
+struct drm_virtgpu_execbuffer_syncobj {
+  __u32 handle;
+  __u32 flags;
+  __u64 point;
+};
 struct drm_virtgpu_execbuffer {
   __u32 flags;
   __u32 size;
@@ -50,7 +57,11 @@
   __u32 num_bo_handles;
   __s32 fence_fd;
   __u32 ring_idx;
-  __u32 pad;
+  __u32 syncobj_stride;
+  __u32 num_in_syncobjs;
+  __u32 num_out_syncobjs;
+  __u64 in_syncobjs;
+  __u64 out_syncobjs;
 };
 #define VIRTGPU_PARAM_3D_FEATURES 1
 #define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2