Merge "riscv64 <sys/user.h>."
diff --git a/libc/Android.bp b/libc/Android.bp
index d985c81..e59fac2 100644
--- a/libc/Android.bp
+++ b/libc/Android.bp
@@ -1921,6 +1921,9 @@
         arm64: {
             export_system_include_dirs: ["kernel/uapi/asm-arm64"],
         },
+        riscv64: {
+            export_system_include_dirs: ["kernel/uapi/asm-riscv"],
+        },
         x86: {
             export_system_include_dirs: ["kernel/uapi/asm-x86"],
         },
diff --git a/libc/include/bits/fenv_riscv64.h b/libc/include/bits/fenv_riscv64.h
new file mode 100644
index 0000000..e1e43b6
--- /dev/null
+++ b/libc/include/bits/fenv_riscv64.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2022 The Android Open Source Project
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#pragma once
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+typedef __uint32_t fenv_t;
+typedef __uint32_t fexcept_t;
+
+/* Exception flags. No FE_DENORMAL for riscv64. */
+#define FE_INEXACT    0x01
+#define FE_UNDERFLOW  0x02
+#define FE_OVERFLOW   0x04
+#define FE_DIVBYZERO  0x08
+#define FE_INVALID    0x10
+#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW)
+
+/* Rounding modes. */
+#define FE_TONEAREST  0x0
+#define FE_TOWARDZERO 0x1
+#define FE_DOWNWARD   0x2
+#define FE_UPWARD     0x3
+
+__END_DECLS
diff --git a/libc/include/fenv.h b/libc/include/fenv.h
index 7b775b6..3fd9852 100644
--- a/libc/include/fenv.h
+++ b/libc/include/fenv.h
@@ -35,6 +35,8 @@
 #include <bits/fenv_arm.h>
 #elif defined(__i386__)
 #include <bits/fenv_x86.h>
+#elif defined(__riscv)
+#include <bits/fenv_riscv64.h>
 #elif defined(__x86_64__)
 #include <bits/fenv_x86_64.h>
 #endif
diff --git a/libc/platform/bionic/macros.h b/libc/platform/bionic/macros.h
index 076cff1..9e13e0d 100644
--- a/libc/platform/bionic/macros.h
+++ b/libc/platform/bionic/macros.h
@@ -55,6 +55,8 @@
 #define BIONIC_STOP_UNWIND asm volatile(".cfi_undefined x30")
 #elif defined(__i386__)
 #define BIONIC_STOP_UNWIND asm volatile(".cfi_undefined \%eip")
+#elif defined(__riscv)
+#define BIONIC_STOP_UNWIND asm volatile(".cfi_undefined ra")
 #elif defined(__x86_64__)
 #define BIONIC_STOP_UNWIND asm volatile(".cfi_undefined \%rip")
 #endif
diff --git a/libc/platform/bionic/tls.h b/libc/platform/bionic/tls.h
index bf9e65b..e01eccd 100644
--- a/libc/platform/bionic/tls.h
+++ b/libc/platform/bionic/tls.h
@@ -34,6 +34,8 @@
 # define __get_tls() ({ void** __val; __asm__("mrc p15, 0, %0, c13, c0, 3" : "=r"(__val)); __val; })
 #elif defined(__i386__)
 # define __get_tls() ({ void** __val; __asm__("movl %%gs:0, %0" : "=r"(__val)); __val; })
+#elif defined(__riscv)
+# define __get_tls() ({ void** __val; __asm__("mv %0, tp" : "=r"(__val)); __val; })
 #elif defined(__x86_64__)
 # define __get_tls() ({ void** __val; __asm__("mov %%fs:0, %0" : "=r"(__val)); __val; })
 #else