diff --git a/libc/kernel/uapi/drm/amdgpu_drm.h b/libc/kernel/uapi/drm/amdgpu_drm.h
index e1768c6..f5e8b16 100644
--- a/libc/kernel/uapi/drm/amdgpu_drm.h
+++ b/libc/kernel/uapi/drm/amdgpu_drm.h
@@ -149,8 +149,10 @@
 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3
 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21
 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3
-#define AMDGPU_TILING_SET(field,value) (((value) & AMDGPU_TILING_ ##field ##_MASK) << AMDGPU_TILING_ ##field ##_SHIFT)
-#define AMDGPU_TILING_GET(value,field) (((value) >> AMDGPU_TILING_ ##field ##_SHIFT) & AMDGPU_TILING_ ##field ##_MASK)
+#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
+#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
+#define AMDGPU_TILING_SET(field,value) (((__u64) (value) & AMDGPU_TILING_ ##field ##_MASK) << AMDGPU_TILING_ ##field ##_SHIFT)
+#define AMDGPU_TILING_GET(value,field) (((__u64) (value) >> AMDGPU_TILING_ ##field ##_SHIFT) & AMDGPU_TILING_ ##field ##_MASK)
 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2
 struct drm_amdgpu_gem_metadata {
@@ -232,10 +234,19 @@
 };
 #define AMDGPU_VA_OP_MAP 1
 #define AMDGPU_VA_OP_UNMAP 2
+#define AMDGPU_VA_OP_CLEAR 3
+#define AMDGPU_VA_OP_REPLACE 4
 #define AMDGPU_VM_DELAY_UPDATE (1 << 0)
 #define AMDGPU_VM_PAGE_READABLE (1 << 1)
 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2)
 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
+#define AMDGPU_VM_PAGE_PRT (1 << 4)
+#define AMDGPU_VM_MTYPE_MASK (0xf << 5)
+#define AMDGPU_VM_MTYPE_DEFAULT (0 << 5)
+#define AMDGPU_VM_MTYPE_NC (1 << 5)
+#define AMDGPU_VM_MTYPE_WC (2 << 5)
+#define AMDGPU_VM_MTYPE_CC (3 << 5)
+#define AMDGPU_VM_MTYPE_UC (4 << 5)
 struct drm_amdgpu_gem_va {
   __u32 handle;
   __u32 _pad;
@@ -250,7 +261,8 @@
 #define AMDGPU_HW_IP_DMA 2
 #define AMDGPU_HW_IP_UVD 3
 #define AMDGPU_HW_IP_VCE 4
-#define AMDGPU_HW_IP_NUM 5
+#define AMDGPU_HW_IP_UVD_ENC 5
+#define AMDGPU_HW_IP_NUM 6
 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
 #define AMDGPU_CHUNK_ID_IB 0x01
 #define AMDGPU_CHUNK_ID_FENCE 0x02
@@ -276,6 +288,7 @@
 };
 #define AMDGPU_IB_FLAG_CE (1 << 0)
 #define AMDGPU_IB_FLAG_PREAMBLE (1 << 1)
+#define AMDGPU_IB_FLAG_PREEMPT (1 << 2)
 struct drm_amdgpu_cs_chunk_ib {
   __u32 _pad;
   __u32 flags;
@@ -320,6 +333,8 @@
 #define AMDGPU_INFO_FW_GFX_MEC 0x08
 #define AMDGPU_INFO_FW_SMC 0x0a
 #define AMDGPU_INFO_FW_SDMA 0x0b
+#define AMDGPU_INFO_FW_SOS 0x0c
+#define AMDGPU_INFO_FW_ASD 0x0d
 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
 #define AMDGPU_INFO_VRAM_USAGE 0x10
 #define AMDGPU_INFO_GTT_USAGE 0x11
@@ -334,6 +349,15 @@
 #define AMDGPU_INFO_VBIOS 0x1B
 #define AMDGPU_INFO_VBIOS_SIZE 0x1
 #define AMDGPU_INFO_VBIOS_IMAGE 0x2
+#define AMDGPU_INFO_NUM_HANDLES 0x1C
+#define AMDGPU_INFO_SENSOR 0x1D
+#define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1
+#define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2
+#define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3
+#define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4
+#define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5
+#define AMDGPU_INFO_SENSOR_VDDNB 0x6
+#define AMDGPU_INFO_SENSOR_VDDGFX 0x7
 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
@@ -368,6 +392,9 @@
       __u32 type;
       __u32 offset;
     } vbios_info;
+    struct {
+      __u32 type;
+    } sensor_info;
   };
 };
 struct drm_amdgpu_info_gds {
@@ -436,6 +463,23 @@
   __u32 vram_type;
   __u32 vram_bit_width;
   __u32 vce_harvest_config;
+  __u32 gc_double_offchip_lds_buf;
+  __u64 prim_buf_gpu_addr;
+  __u64 pos_buf_gpu_addr;
+  __u64 cntl_sb_buf_gpu_addr;
+  __u64 param_buf_gpu_addr;
+  __u32 prim_buf_size;
+  __u32 pos_buf_size;
+  __u32 cntl_sb_buf_size;
+  __u32 param_buf_size;
+  __u32 wave_front_size;
+  __u32 num_shader_visible_vgprs;
+  __u32 num_cu_per_sh;
+  __u32 num_tcc_blocks;
+  __u32 gs_vgt_table_depth;
+  __u32 gs_prim_buffer_depth;
+  __u32 max_gs_waves_per_vgt;
+  __u32 _pad1;
 };
 struct drm_amdgpu_info_hw_ip {
   __u32 hw_ip_version_major;
@@ -446,6 +490,10 @@
   __u32 available_rings;
   __u32 _pad;
 };
+struct drm_amdgpu_info_num_handles {
+  __u32 uvd_max_handles;
+  __u32 uvd_used_handles;
+};
 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6
 struct drm_amdgpu_info_vce_clock_table_entry {
   __u32 sclk;
@@ -464,6 +512,7 @@
 #define AMDGPU_FAMILY_KV 125
 #define AMDGPU_FAMILY_VI 130
 #define AMDGPU_FAMILY_CZ 135
+#define AMDGPU_FAMILY_AI 141
 #ifdef __cplusplus
 #endif
 #endif
diff --git a/libc/kernel/uapi/drm/drm.h b/libc/kernel/uapi/drm/drm.h
index d28c054..251deeb 100644
--- a/libc/kernel/uapi/drm/drm.h
+++ b/libc/kernel/uapi/drm/drm.h
@@ -360,6 +360,7 @@
 #define DRM_CAP_CURSOR_HEIGHT 0x9
 #define DRM_CAP_ADDFB2_MODIFIERS 0x10
 #define DRM_CAP_PAGE_FLIP_TARGET 0x11
+#define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12
 struct drm_get_cap {
   __u64 capability;
   __u64 value;
@@ -490,7 +491,7 @@
   __u32 tv_sec;
   __u32 tv_usec;
   __u32 sequence;
-  __u32 reserved;
+  __u32 crtc_id;
 };
 typedef struct drm_clip_rect drm_clip_rect_t;
 typedef struct drm_drawable_info drm_drawable_info_t;
diff --git a/libc/kernel/uapi/drm/drm_fourcc.h b/libc/kernel/uapi/drm/drm_fourcc.h
index 0747742..630ad30 100644
--- a/libc/kernel/uapi/drm/drm_fourcc.h
+++ b/libc/kernel/uapi/drm/drm_fourcc.h
@@ -25,8 +25,11 @@
 #define DRM_FORMAT_BIG_ENDIAN (1 << 31)
 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ')
 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ')
+#define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ')
 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8')
 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8')
+#define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2')
+#define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2')
 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8')
 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8')
 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2')
@@ -70,6 +73,14 @@
 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y')
 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y')
 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V')
+#define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
+#define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
+#define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
+#define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
+#define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
+#define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
+#define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
+#define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2')
 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1')
 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6')
@@ -87,16 +98,29 @@
 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4')
 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4')
 #define DRM_FORMAT_MOD_NONE 0
+#define DRM_FORMAT_MOD_VENDOR_NONE 0
 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02
 #define DRM_FORMAT_MOD_VENDOR_NV 0x03
 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
+#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
 #define fourcc_mod_code(vendor,val) ((((__u64) DRM_FORMAT_MOD_VENDOR_ ##vendor) << 56) | (val & 0x00ffffffffffffffULL))
+#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
+#define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
+#define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
+#define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
+#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
+#define __fourcc_mod_tegra_mode_shift 32
+#define fourcc_mod_tegra_code(val,params) fourcc_mod_code(NV, ((((__u64) val) << __fourcc_mod_tegra_mode_shift) | params))
+#define fourcc_mod_tegra_mod(m) (m & ~((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
+#define fourcc_mod_tegra_param(m) (m & ((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
+#define NV_FORMAT_MOD_TEGRA_TILED fourcc_mod_tegra_code(1, 0)
+#define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v)
 #ifdef __cplusplus
 #endif
 #endif
diff --git a/libc/kernel/uapi/drm/drm_mode.h b/libc/kernel/uapi/drm/drm_mode.h
index f15f3c6..9e7ee92 100644
--- a/libc/kernel/uapi/drm/drm_mode.h
+++ b/libc/kernel/uapi/drm/drm_mode.h
@@ -77,6 +77,8 @@
 #define DRM_MODE_DIRTY_OFF 0
 #define DRM_MODE_DIRTY_ON 1
 #define DRM_MODE_DIRTY_ANNOTATE 2
+#define DRM_MODE_LINK_STATUS_GOOD 0
+#define DRM_MODE_LINK_STATUS_BAD 1
 struct drm_mode_modeinfo {
   __u32 clock;
   __u16 hdisplay;
diff --git a/libc/kernel/uapi/drm/etnaviv_drm.h b/libc/kernel/uapi/drm/etnaviv_drm.h
index 04a1640..6376e25 100644
--- a/libc/kernel/uapi/drm/etnaviv_drm.h
+++ b/libc/kernel/uapi/drm/etnaviv_drm.h
@@ -91,6 +91,10 @@
   __u32 handle;
   __u64 presumed;
 };
+#define ETNA_SUBMIT_NO_IMPLICIT 0x0001
+#define ETNA_SUBMIT_FENCE_FD_IN 0x0002
+#define ETNA_SUBMIT_FENCE_FD_OUT 0x0004
+#define ETNA_SUBMIT_FLAGS (ETNA_SUBMIT_NO_IMPLICIT | ETNA_SUBMIT_FENCE_FD_IN | ETNA_SUBMIT_FENCE_FD_OUT)
 #define ETNA_PIPE_3D 0x00
 #define ETNA_PIPE_2D 0x01
 #define ETNA_PIPE_VG 0x02
@@ -104,6 +108,8 @@
   __u64 bos;
   __u64 relocs;
   __u64 stream;
+  __u32 flags;
+  __s32 fence_fd;
 };
 #define ETNA_WAIT_NONBLOCK 0x01
 struct drm_etnaviv_wait_fence {
diff --git a/libc/kernel/uapi/drm/i915_drm.h b/libc/kernel/uapi/drm/i915_drm.h
index 3279d26..af6f064 100644
--- a/libc/kernel/uapi/drm/i915_drm.h
+++ b/libc/kernel/uapi/drm/i915_drm.h
@@ -158,6 +158,7 @@
 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27
 #define DRM_I915_OVERLAY_ATTRS 0x28
 #define DRM_I915_GEM_EXECBUFFER2 0x29
+#define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2
 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a
 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b
 #define DRM_I915_GEM_WAIT 0x2c
@@ -170,6 +171,7 @@
 #define DRM_I915_GEM_USERPTR 0x33
 #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
 #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
+#define DRM_I915_PERF_OPEN 0x36
 #define DRM_IOCTL_I915_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLUSH)
 #define DRM_IOCTL_I915_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLIP)
@@ -190,6 +192,7 @@
 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
+#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)
 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
@@ -222,6 +225,7 @@
 #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
 #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
 #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
+#define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
 typedef struct drm_i915_batchbuffer {
   int start;
   int used;
@@ -285,6 +289,9 @@
 #define I915_PARAM_MIN_EU_IN_POOL 39
 #define I915_PARAM_MMAP_GTT_VERSION 40
 #define I915_PARAM_HAS_SCHEDULER 41
+#define I915_PARAM_HUC_STATUS 42
+#define I915_PARAM_HAS_EXEC_ASYNC 43
+#define I915_PARAM_HAS_EXEC_FENCE 44
 typedef struct drm_i915_getparam {
   __s32 param;
   int __user * value;
@@ -418,7 +425,8 @@
 #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1 << 3)
 #define EXEC_OBJECT_PINNED (1 << 4)
 #define EXEC_OBJECT_PAD_TO_SIZE (1 << 5)
-#define __EXEC_OBJECT_UNKNOWN_FLAGS - (EXEC_OBJECT_PAD_TO_SIZE << 1)
+#define EXEC_OBJECT_ASYNC (1 << 6)
+#define __EXEC_OBJECT_UNKNOWN_FLAGS - (EXEC_OBJECT_ASYNC << 1)
   __u64 flags;
   union {
     __u64 rsvd1;
@@ -460,7 +468,9 @@
 #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT)
 #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT)
 #define I915_EXEC_RESOURCE_STREAMER (1 << 15)
-#define __I915_EXEC_UNKNOWN_FLAGS - (I915_EXEC_RESOURCE_STREAMER << 1)
+#define I915_EXEC_FENCE_IN (1 << 16)
+#define I915_EXEC_FENCE_OUT (1 << 17)
+#define __I915_EXEC_UNKNOWN_FLAGS (- (I915_EXEC_FENCE_OUT << 1))
 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
 #define i915_execbuffer2_set_context_id(eb2,context) (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
 #define i915_execbuffer2_get_context_id(eb2) ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
@@ -629,8 +639,48 @@
 #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
 #define I915_CONTEXT_PARAM_GTT_SIZE 0x3
 #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
+#define I915_CONTEXT_PARAM_BANNABLE 0x5
   __u64 value;
 };
+enum drm_i915_oa_format {
+  I915_OA_FORMAT_A13 = 1,
+  I915_OA_FORMAT_A29,
+  I915_OA_FORMAT_A13_B8_C8,
+  I915_OA_FORMAT_B4_C8,
+  I915_OA_FORMAT_A45_B8_C8,
+  I915_OA_FORMAT_B4_C8_A16,
+  I915_OA_FORMAT_C4_B8,
+  I915_OA_FORMAT_MAX
+};
+enum drm_i915_perf_property_id {
+  DRM_I915_PERF_PROP_CTX_HANDLE = 1,
+  DRM_I915_PERF_PROP_SAMPLE_OA,
+  DRM_I915_PERF_PROP_OA_METRICS_SET,
+  DRM_I915_PERF_PROP_OA_FORMAT,
+  DRM_I915_PERF_PROP_OA_EXPONENT,
+  DRM_I915_PERF_PROP_MAX
+};
+struct drm_i915_perf_open_param {
+  __u32 flags;
+#define I915_PERF_FLAG_FD_CLOEXEC (1 << 0)
+#define I915_PERF_FLAG_FD_NONBLOCK (1 << 1)
+#define I915_PERF_FLAG_DISABLED (1 << 2)
+  __u32 num_properties;
+  __u64 properties_ptr;
+};
+#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
+#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
+struct drm_i915_perf_record_header {
+  __u32 type;
+  __u16 pad;
+  __u16 size;
+};
+enum drm_i915_perf_record_type {
+  DRM_I915_PERF_RECORD_SAMPLE = 1,
+  DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2,
+  DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3,
+  DRM_I915_PERF_RECORD_MAX
+};
 #ifdef __cplusplus
 #endif
 #endif
diff --git a/libc/kernel/uapi/drm/msm_drm.h b/libc/kernel/uapi/drm/msm_drm.h
index a8e4943..83ad769 100644
--- a/libc/kernel/uapi/drm/msm_drm.h
+++ b/libc/kernel/uapi/drm/msm_drm.h
@@ -37,6 +37,7 @@
 #define MSM_PARAM_CHIP_ID 0x03
 #define MSM_PARAM_MAX_FREQ 0x04
 #define MSM_PARAM_TIMESTAMP 0x05
+#define MSM_PARAM_GMEM_BASE 0x06
 struct drm_msm_param {
   __u32 pipe;
   __u32 param;
diff --git a/libc/kernel/uapi/drm/omap_drm.h b/libc/kernel/uapi/drm/omap_drm.h
index 2da6420..54b539a 100644
--- a/libc/kernel/uapi/drm/omap_drm.h
+++ b/libc/kernel/uapi/drm/omap_drm.h
@@ -23,8 +23,8 @@
 #endif
 #define OMAP_PARAM_CHIPSET_ID 1
 struct drm_omap_param {
-  uint64_t param;
-  uint64_t value;
+  __u64 param;
+  __u64 value;
 };
 #define OMAP_BO_SCANOUT 0x00000001
 #define OMAP_BO_CACHE_MASK 0x00000006
@@ -37,38 +37,38 @@
 #define OMAP_BO_TILED_32 0x00000300
 #define OMAP_BO_TILED (OMAP_BO_TILED_8 | OMAP_BO_TILED_16 | OMAP_BO_TILED_32)
 union omap_gem_size {
-  uint32_t bytes;
+  __u32 bytes;
   struct {
-    uint16_t width;
-    uint16_t height;
+    __u16 width;
+    __u16 height;
   } tiled;
 };
 struct drm_omap_gem_new {
   union omap_gem_size size;
-  uint32_t flags;
-  uint32_t handle;
-  uint32_t __pad;
+  __u32 flags;
+  __u32 handle;
+  __u32 __pad;
 };
 enum omap_gem_op {
   OMAP_GEM_READ = 0x01,
   OMAP_GEM_WRITE = 0x02,
 };
 struct drm_omap_gem_cpu_prep {
-  uint32_t handle;
-  uint32_t op;
+  __u32 handle;
+  __u32 op;
 };
 struct drm_omap_gem_cpu_fini {
-  uint32_t handle;
-  uint32_t op;
-  uint32_t nregions;
-  uint32_t __pad;
+  __u32 handle;
+  __u32 op;
+  __u32 nregions;
+  __u32 __pad;
 };
 struct drm_omap_gem_info {
-  uint32_t handle;
-  uint32_t pad;
-  uint64_t offset;
-  uint32_t size;
-  uint32_t __pad;
+  __u32 handle;
+  __u32 pad;
+  __u64 offset;
+  __u32 size;
+  __u32 __pad;
 };
 #define DRM_OMAP_GET_PARAM 0x00
 #define DRM_OMAP_SET_PARAM 0x01
diff --git a/libc/kernel/uapi/drm/vmwgfx_drm.h b/libc/kernel/uapi/drm/vmwgfx_drm.h
index a9e6952..2b7e0fe 100644
--- a/libc/kernel/uapi/drm/vmwgfx_drm.h
+++ b/libc/kernel/uapi/drm/vmwgfx_drm.h
@@ -26,6 +26,7 @@
 #define DRM_VMW_GET_PARAM 0
 #define DRM_VMW_ALLOC_DMABUF 1
 #define DRM_VMW_UNREF_DMABUF 2
+#define DRM_VMW_HANDLE_CLOSE 2
 #define DRM_VMW_CURSOR_BYPASS 3
 #define DRM_VMW_CONTROL_STREAM 4
 #define DRM_VMW_CLAIM_STREAM 5
@@ -314,6 +315,10 @@
   enum drm_vmw_extended_context req;
   struct drm_vmw_context_arg rep;
 };
+struct drm_vmw_handle_close_arg {
+  __u32 handle;
+  __u32 pad64;
+};
 #ifdef __cplusplus
 #endif
 #endif