diff --git a/libc/Android.bp b/libc/Android.bp
index 68a0838..267fae2 100644
--- a/libc/Android.bp
+++ b/libc/Android.bp
@@ -951,6 +951,7 @@
                 "arch-riscv64/string/memcpy_vext.S",
                 "arch-riscv64/string/memmove_vext.S",
                 "arch-riscv64/string/memset_vext.S",
+                "arch-riscv64/string/stpcpy_vext.S",
                 "arch-riscv64/string/strcat_vext.S",
                 "arch-riscv64/string/strchr_vext.S",
                 "arch-riscv64/string/strcmp_vext.S",
diff --git a/libc/arch-riscv64/dynamic_function_dispatch.cpp b/libc/arch-riscv64/dynamic_function_dispatch.cpp
index 0925c5f..5866fe4 100644
--- a/libc/arch-riscv64/dynamic_function_dispatch.cpp
+++ b/libc/arch-riscv64/dynamic_function_dispatch.cpp
@@ -58,6 +58,11 @@
   RETURN_FUNC(memset_func, memset_vext);
 }
 
+typedef char* stpcpy_func(char*, const char*);
+DEFINE_IFUNC_FOR(stpcpy) {
+  RETURN_FUNC(stpcpy_func, stpcpy_vext);
+}
+
 typedef char* strcat_func(char*, const char*);
 DEFINE_IFUNC_FOR(strcat) {
   RETURN_FUNC(strcat_func, strcat_vext);
diff --git a/libc/arch-riscv64/static_function_dispatch.S b/libc/arch-riscv64/static_function_dispatch.S
index 3bf0275..f96d40e 100644
--- a/libc/arch-riscv64/static_function_dispatch.S
+++ b/libc/arch-riscv64/static_function_dispatch.S
@@ -40,6 +40,7 @@
 FUNCTION_DELEGATE(memcpy, memcpy_vext)
 FUNCTION_DELEGATE(memmove, memmove_vext)
 FUNCTION_DELEGATE(memset, memset_vext)
+FUNCTION_DELEGATE(stpcpy, stpcpy_vext)
 FUNCTION_DELEGATE(strcat, strcat_vext)
 FUNCTION_DELEGATE(strchr, strchr_vext)
 FUNCTION_DELEGATE(strcmp, strcmp_vext)
diff --git a/libc/arch-riscv64/string/stpcpy_vext.S b/libc/arch-riscv64/string/stpcpy_vext.S
new file mode 100644
index 0000000..3096e76
--- /dev/null
+++ b/libc/arch-riscv64/string/stpcpy_vext.S
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2023 The Android Open Source Project
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+/*
+ * Copyright (c) 2023 SiFive, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the company may not be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY SIFIVE INC ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL SIFIVE INC BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if defined(__riscv_v)
+
+#include <private/bionic_asm.h>
+
+#define pDstPtr a0
+#define pSrc a1
+
+#define iVL a3
+#define iCurrentVL a4
+#define iActiveElemPos a5
+
+#define ELEM_LMUL_SETTING m1
+#define vMask1 v0
+#define vMask2 v1
+#define vStr1 v8
+#define vStr2 v16
+
+ENTRY(stpcpy_vext)
+L(stpcpy_loop):
+    vsetvli iVL, zero, e8, ELEM_LMUL_SETTING, ta, ma
+    vle8ff.v vStr1, (pSrc)
+    vmseq.vx vMask2, vStr1, zero
+    csrr iCurrentVL, vl
+    vfirst.m iActiveElemPos, vMask2
+    vmsif.m vMask1, vMask2
+    add pSrc, pSrc, iCurrentVL
+    vse8.v vStr1, (pDstPtr), vMask1.t
+    add pDstPtr, pDstPtr, iCurrentVL
+    bltz iActiveElemPos, L(stpcpy_loop)
+
+    // stpcpy() returns a pointer to the '\0', not the byte after it.
+    addi pDstPtr, pDstPtr, -1
+    ret
+END(stpcpy_vext)
+
+#endif