Add Silvermont architecture cache sizes
Adds Silvermont specific cache sizes for bionic optimizations.
Change-Id: Ib992f530b8c485121b2874470fd6bed2212adb0f
Signed-off-by: Henrik Smiding <henrik.smiding@intel.com>
diff --git a/libc/arch-x86/string/cache.h b/libc/arch-x86/string/cache.h
index d9aff5c..9d0a563 100644
--- a/libc/arch-x86/string/cache.h
+++ b/libc/arch-x86/string/cache.h
@@ -28,8 +28,15 @@
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#if defined(__slm__)
+/* Values are optimized for Silvermont */
+#define SHARED_CACHE_SIZE (1024*1024) /* Silvermont L2 Cache */
+#define DATA_CACHE_SIZE (24*1024) /* Silvermont L1 Data Cache */
+#else
/* Values are optimized for Atom */
#define SHARED_CACHE_SIZE (512*1024) /* Atom L2 Cache */
#define DATA_CACHE_SIZE (24*1024) /* Atom L1 Data Cache */
+#endif
+
#define SHARED_CACHE_SIZE_HALF (SHARED_CACHE_SIZE / 2)
#define DATA_CACHE_SIZE_HALF (DATA_CACHE_SIZE / 2)