diff --git a/libc/kernel/uapi/drm/drm_fourcc.h b/libc/kernel/uapi/drm/drm_fourcc.h
index 099791c..aaa94cd 100644
--- a/libc/kernel/uapi/drm/drm_fourcc.h
+++ b/libc/kernel/uapi/drm/drm_fourcc.h
@@ -207,6 +207,15 @@
 #define AFBC_FORMAT_MOD_DB (1ULL << 10)
 #define AFBC_FORMAT_MOD_BCH (1ULL << 11)
 #define AFBC_FORMAT_MOD_USM (1ULL << 12)
+#define DRM_FORMAT_MOD_ARM_TYPE_AFRC 0x02
+#define DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode)
+#define AFRC_FORMAT_MOD_CU_SIZE_MASK 0xf
+#define AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL)
+#define AFRC_FORMAT_MOD_CU_SIZE_24 (2ULL)
+#define AFRC_FORMAT_MOD_CU_SIZE_32 (3ULL)
+#define AFRC_FORMAT_MOD_CU_SIZE_P0(__afrc_cu_size) (__afrc_cu_size)
+#define AFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4)
+#define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8)
 #define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
 #define __fourcc_mod_amlogic_layout_mask 0xff
diff --git a/libc/kernel/uapi/drm/i915_drm.h b/libc/kernel/uapi/drm/i915_drm.h
index 225c1da..9e56f4c 100644
--- a/libc/kernel/uapi/drm/i915_drm.h
+++ b/libc/kernel/uapi/drm/i915_drm.h
@@ -351,6 +351,7 @@
 #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
 #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
 #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
+#define I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 5)
 #define I915_PARAM_HUC_STATUS 42
 #define I915_PARAM_HAS_EXEC_ASYNC 43
 #define I915_PARAM_HAS_EXEC_FENCE 44
@@ -365,6 +366,7 @@
 #define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
 #define I915_PARAM_PERF_REVISION 54
 #define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55
+#define I915_PARAM_HAS_USERPTR_PROBE 56
 typedef struct drm_i915_getparam {
   __s32 param;
   int __user * value;
@@ -455,6 +457,7 @@
 #define I915_MMAP_OFFSET_WC 1
 #define I915_MMAP_OFFSET_WB 2
 #define I915_MMAP_OFFSET_UC 3
+#define I915_MMAP_OFFSET_FIXED 4
   __u64 extensions;
 };
 struct drm_i915_gem_set_domain {
@@ -592,11 +595,11 @@
   __u32 handle;
   __u32 busy;
 };
+struct drm_i915_gem_caching {
+  __u32 handle;
 #define I915_CACHING_NONE 0
 #define I915_CACHING_CACHED 1
 #define I915_CACHING_DISPLAY 2
-struct drm_i915_gem_caching {
-  __u32 handle;
   __u32 caching;
 };
 #define I915_TILING_NONE 0
@@ -784,20 +787,7 @@
   struct i915_user_extension base;
   struct drm_i915_gem_context_param param;
 };
-struct drm_i915_gem_context_create_ext_clone {
 #define I915_CONTEXT_CREATE_EXT_CLONE 1
-  struct i915_user_extension base;
-  __u32 clone_id;
-  __u32 flags;
-#define I915_CONTEXT_CLONE_ENGINES (1u << 0)
-#define I915_CONTEXT_CLONE_FLAGS (1u << 1)
-#define I915_CONTEXT_CLONE_SCHEDATTR (1u << 2)
-#define I915_CONTEXT_CLONE_SSEU (1u << 3)
-#define I915_CONTEXT_CLONE_TIMELINE (1u << 4)
-#define I915_CONTEXT_CLONE_VM (1u << 5)
-#define I915_CONTEXT_CLONE_UNKNOWN - (I915_CONTEXT_CLONE_VM << 1)
-  __u64 rsvd;
-};
 struct drm_i915_gem_context_destroy {
   __u32 ctx_id;
   __u32 pad;
@@ -825,6 +815,7 @@
   __u64 user_size;
   __u32 flags;
 #define I915_USERPTR_READ_ONLY 0x1
+#define I915_USERPTR_PROBE 0x2
 #define I915_USERPTR_UNSYNCHRONIZED 0x80000000
   __u32 handle;
 };
diff --git a/libc/kernel/uapi/drm/msm_drm.h b/libc/kernel/uapi/drm/msm_drm.h
index 5aabc18..b4ba1d0 100644
--- a/libc/kernel/uapi/drm/msm_drm.h
+++ b/libc/kernel/uapi/drm/msm_drm.h
@@ -39,10 +39,11 @@
 #define MSM_PARAM_MAX_FREQ 0x04
 #define MSM_PARAM_TIMESTAMP 0x05
 #define MSM_PARAM_GMEM_BASE 0x06
-#define MSM_PARAM_NR_RINGS 0x07
+#define MSM_PARAM_PRIORITIES 0x07
 #define MSM_PARAM_PP_PGTABLE 0x08
 #define MSM_PARAM_FAULTS 0x09
 #define MSM_PARAM_SUSPENDS 0x0a
+#define MSM_PARAM_NR_RINGS MSM_PARAM_PRIORITIES
 struct drm_msm_param {
   __u32 pipe;
   __u32 param;
diff --git a/libc/kernel/uapi/drm/tegra_drm.h b/libc/kernel/uapi/drm/tegra_drm.h
index 5244a27..5e90635 100644
--- a/libc/kernel/uapi/drm/tegra_drm.h
+++ b/libc/kernel/uapi/drm/tegra_drm.h
@@ -163,6 +163,104 @@
 #define DRM_IOCTL_TEGRA_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling)
 #define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags)
 #define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags)
+#define DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT (1 << 0)
+struct drm_tegra_channel_open {
+  __u32 host1x_class;
+  __u32 flags;
+  __u32 context;
+  __u32 version;
+  __u32 capabilities;
+  __u32 padding;
+};
+struct drm_tegra_channel_close {
+  __u32 context;
+  __u32 padding;
+};
+#define DRM_TEGRA_CHANNEL_MAP_READ (1 << 0)
+#define DRM_TEGRA_CHANNEL_MAP_WRITE (1 << 1)
+#define DRM_TEGRA_CHANNEL_MAP_READ_WRITE (DRM_TEGRA_CHANNEL_MAP_READ | DRM_TEGRA_CHANNEL_MAP_WRITE)
+struct drm_tegra_channel_map {
+  __u32 context;
+  __u32 handle;
+  __u32 flags;
+  __u32 mapping;
+};
+struct drm_tegra_channel_unmap {
+  __u32 context;
+  __u32 mapping;
+};
+#define DRM_TEGRA_SUBMIT_RELOC_SECTOR_LAYOUT (1 << 0)
+struct drm_tegra_submit_buf {
+  __u32 mapping;
+  __u32 flags;
+  struct {
+    __u64 target_offset;
+    __u32 gather_offset_words;
+    __u32 shift;
+  } reloc;
+};
+#define DRM_TEGRA_SUBMIT_CMD_GATHER_UPTR 0
+#define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT 1
+#define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT_RELATIVE 2
+struct drm_tegra_submit_cmd_gather_uptr {
+  __u32 words;
+  __u32 reserved[3];
+};
+struct drm_tegra_submit_cmd_wait_syncpt {
+  __u32 id;
+  __u32 value;
+  __u32 reserved[2];
+};
+struct drm_tegra_submit_cmd {
+  __u32 type;
+  __u32 flags;
+  union {
+    struct drm_tegra_submit_cmd_gather_uptr gather_uptr;
+    struct drm_tegra_submit_cmd_wait_syncpt wait_syncpt;
+    __u32 reserved[4];
+  };
+};
+struct drm_tegra_submit_syncpt {
+  __u32 id;
+  __u32 flags;
+  __u32 increments;
+  __u32 value;
+};
+struct drm_tegra_channel_submit {
+  __u32 context;
+  __u32 num_bufs;
+  __u32 num_cmds;
+  __u32 gather_data_words;
+  __u64 bufs_ptr;
+  __u64 cmds_ptr;
+  __u64 gather_data_ptr;
+  __u32 syncobj_in;
+  __u32 syncobj_out;
+  struct drm_tegra_submit_syncpt syncpt;
+};
+struct drm_tegra_syncpoint_allocate {
+  __u32 id;
+  __u32 padding;
+};
+struct drm_tegra_syncpoint_free {
+  __u32 id;
+  __u32 padding;
+};
+struct drm_tegra_syncpoint_wait {
+  __s64 timeout_ns;
+  __u32 id;
+  __u32 threshold;
+  __u32 value;
+  __u32 padding;
+};
+#define DRM_IOCTL_TEGRA_CHANNEL_OPEN DRM_IOWR(DRM_COMMAND_BASE + 0x10, struct drm_tegra_channel_open)
+#define DRM_IOCTL_TEGRA_CHANNEL_CLOSE DRM_IOWR(DRM_COMMAND_BASE + 0x11, struct drm_tegra_channel_close)
+#define DRM_IOCTL_TEGRA_CHANNEL_MAP DRM_IOWR(DRM_COMMAND_BASE + 0x12, struct drm_tegra_channel_map)
+#define DRM_IOCTL_TEGRA_CHANNEL_UNMAP DRM_IOWR(DRM_COMMAND_BASE + 0x13, struct drm_tegra_channel_unmap)
+#define DRM_IOCTL_TEGRA_CHANNEL_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + 0x14, struct drm_tegra_channel_submit)
+#define DRM_IOCTL_TEGRA_SYNCPOINT_ALLOCATE DRM_IOWR(DRM_COMMAND_BASE + 0x20, struct drm_tegra_syncpoint_allocate)
+#define DRM_IOCTL_TEGRA_SYNCPOINT_FREE DRM_IOWR(DRM_COMMAND_BASE + 0x21, struct drm_tegra_syncpoint_free)
+#define DRM_IOCTL_TEGRA_SYNCPOINT_WAIT DRM_IOWR(DRM_COMMAND_BASE + 0x22, struct drm_tegra_syncpoint_wait)
 #ifdef __cplusplus
 }
 #endif
diff --git a/libc/kernel/uapi/drm/v3d_drm.h b/libc/kernel/uapi/drm/v3d_drm.h
index cdc2cf5..a393e5d 100644
--- a/libc/kernel/uapi/drm/v3d_drm.h
+++ b/libc/kernel/uapi/drm/v3d_drm.h
@@ -30,6 +30,9 @@
 #define DRM_V3D_GET_BO_OFFSET 0x05
 #define DRM_V3D_SUBMIT_TFU 0x06
 #define DRM_V3D_SUBMIT_CSD 0x07
+#define DRM_V3D_PERFMON_CREATE 0x08
+#define DRM_V3D_PERFMON_DESTROY 0x09
+#define DRM_V3D_PERFMON_GET_VALUES 0x0a
 #define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
 #define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
 #define DRM_IOCTL_V3D_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_CREATE_BO, struct drm_v3d_create_bo)
@@ -38,6 +41,9 @@
 #define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
 #define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
 #define DRM_IOCTL_V3D_SUBMIT_CSD DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd)
+#define DRM_IOCTL_V3D_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_CREATE, struct drm_v3d_perfmon_create)
+#define DRM_IOCTL_V3D_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_DESTROY, struct drm_v3d_perfmon_destroy)
+#define DRM_IOCTL_V3D_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_VALUES, struct drm_v3d_perfmon_get_values)
 #define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x01
 struct drm_v3d_submit_cl {
   __u32 bcl_start;
@@ -53,6 +59,8 @@
   __u64 bo_handles;
   __u32 bo_handle_count;
   __u32 flags;
+  __u32 perfmon_id;
+  __u32 pad;
 };
 struct drm_v3d_wait_bo {
   __u32 handle;
@@ -81,6 +89,7 @@
   DRM_V3D_PARAM_SUPPORTS_TFU,
   DRM_V3D_PARAM_SUPPORTS_CSD,
   DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH,
+  DRM_V3D_PARAM_SUPPORTS_PERFMON,
 };
 struct drm_v3d_get_param {
   __u32 param;
@@ -111,6 +120,111 @@
   __u32 bo_handle_count;
   __u32 in_sync;
   __u32 out_sync;
+  __u32 perfmon_id;
+};
+enum {
+  V3D_PERFCNT_FEP_VALID_PRIMTS_NO_PIXELS,
+  V3D_PERFCNT_FEP_VALID_PRIMS,
+  V3D_PERFCNT_FEP_EZ_NFCLIP_QUADS,
+  V3D_PERFCNT_FEP_VALID_QUADS,
+  V3D_PERFCNT_TLB_QUADS_STENCIL_FAIL,
+  V3D_PERFCNT_TLB_QUADS_STENCILZ_FAIL,
+  V3D_PERFCNT_TLB_QUADS_STENCILZ_PASS,
+  V3D_PERFCNT_TLB_QUADS_ZERO_COV,
+  V3D_PERFCNT_TLB_QUADS_NONZERO_COV,
+  V3D_PERFCNT_TLB_QUADS_WRITTEN,
+  V3D_PERFCNT_PTB_PRIM_VIEWPOINT_DISCARD,
+  V3D_PERFCNT_PTB_PRIM_CLIP,
+  V3D_PERFCNT_PTB_PRIM_REV,
+  V3D_PERFCNT_QPU_IDLE_CYCLES,
+  V3D_PERFCNT_QPU_ACTIVE_CYCLES_VERTEX_COORD_USER,
+  V3D_PERFCNT_QPU_ACTIVE_CYCLES_FRAG,
+  V3D_PERFCNT_QPU_CYCLES_VALID_INSTR,
+  V3D_PERFCNT_QPU_CYCLES_TMU_STALL,
+  V3D_PERFCNT_QPU_CYCLES_SCOREBOARD_STALL,
+  V3D_PERFCNT_QPU_CYCLES_VARYINGS_STALL,
+  V3D_PERFCNT_QPU_IC_HIT,
+  V3D_PERFCNT_QPU_IC_MISS,
+  V3D_PERFCNT_QPU_UC_HIT,
+  V3D_PERFCNT_QPU_UC_MISS,
+  V3D_PERFCNT_TMU_TCACHE_ACCESS,
+  V3D_PERFCNT_TMU_TCACHE_MISS,
+  V3D_PERFCNT_VPM_VDW_STALL,
+  V3D_PERFCNT_VPM_VCD_STALL,
+  V3D_PERFCNT_BIN_ACTIVE,
+  V3D_PERFCNT_RDR_ACTIVE,
+  V3D_PERFCNT_L2T_HITS,
+  V3D_PERFCNT_L2T_MISSES,
+  V3D_PERFCNT_CYCLE_COUNT,
+  V3D_PERFCNT_QPU_CYCLES_STALLED_VERTEX_COORD_USER,
+  V3D_PERFCNT_QPU_CYCLES_STALLED_FRAGMENT,
+  V3D_PERFCNT_PTB_PRIMS_BINNED,
+  V3D_PERFCNT_AXI_WRITES_WATCH_0,
+  V3D_PERFCNT_AXI_READS_WATCH_0,
+  V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_0,
+  V3D_PERFCNT_AXI_READ_STALLS_WATCH_0,
+  V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_0,
+  V3D_PERFCNT_AXI_READ_BYTES_WATCH_0,
+  V3D_PERFCNT_AXI_WRITES_WATCH_1,
+  V3D_PERFCNT_AXI_READS_WATCH_1,
+  V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_1,
+  V3D_PERFCNT_AXI_READ_STALLS_WATCH_1,
+  V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_1,
+  V3D_PERFCNT_AXI_READ_BYTES_WATCH_1,
+  V3D_PERFCNT_TLB_PARTIAL_QUADS,
+  V3D_PERFCNT_TMU_CONFIG_ACCESSES,
+  V3D_PERFCNT_L2T_NO_ID_STALL,
+  V3D_PERFCNT_L2T_COM_QUE_STALL,
+  V3D_PERFCNT_L2T_TMU_WRITES,
+  V3D_PERFCNT_TMU_ACTIVE_CYCLES,
+  V3D_PERFCNT_TMU_STALLED_CYCLES,
+  V3D_PERFCNT_CLE_ACTIVE,
+  V3D_PERFCNT_L2T_TMU_READS,
+  V3D_PERFCNT_L2T_CLE_READS,
+  V3D_PERFCNT_L2T_VCD_READS,
+  V3D_PERFCNT_L2T_TMUCFG_READS,
+  V3D_PERFCNT_L2T_SLC0_READS,
+  V3D_PERFCNT_L2T_SLC1_READS,
+  V3D_PERFCNT_L2T_SLC2_READS,
+  V3D_PERFCNT_L2T_TMU_W_MISSES,
+  V3D_PERFCNT_L2T_TMU_R_MISSES,
+  V3D_PERFCNT_L2T_CLE_MISSES,
+  V3D_PERFCNT_L2T_VCD_MISSES,
+  V3D_PERFCNT_L2T_TMUCFG_MISSES,
+  V3D_PERFCNT_L2T_SLC0_MISSES,
+  V3D_PERFCNT_L2T_SLC1_MISSES,
+  V3D_PERFCNT_L2T_SLC2_MISSES,
+  V3D_PERFCNT_CORE_MEM_WRITES,
+  V3D_PERFCNT_L2T_MEM_WRITES,
+  V3D_PERFCNT_PTB_MEM_WRITES,
+  V3D_PERFCNT_TLB_MEM_WRITES,
+  V3D_PERFCNT_CORE_MEM_READS,
+  V3D_PERFCNT_L2T_MEM_READS,
+  V3D_PERFCNT_PTB_MEM_READS,
+  V3D_PERFCNT_PSE_MEM_READS,
+  V3D_PERFCNT_TLB_MEM_READS,
+  V3D_PERFCNT_GMP_MEM_READS,
+  V3D_PERFCNT_PTB_W_MEM_WORDS,
+  V3D_PERFCNT_TLB_W_MEM_WORDS,
+  V3D_PERFCNT_PSE_R_MEM_WORDS,
+  V3D_PERFCNT_TLB_R_MEM_WORDS,
+  V3D_PERFCNT_TMU_MRU_HITS,
+  V3D_PERFCNT_COMPUTE_ACTIVE,
+  V3D_PERFCNT_NUM,
+};
+#define DRM_V3D_MAX_PERF_COUNTERS 32
+struct drm_v3d_perfmon_create {
+  __u32 id;
+  __u32 ncounters;
+  __u8 counters[DRM_V3D_MAX_PERF_COUNTERS];
+};
+struct drm_v3d_perfmon_destroy {
+  __u32 id;
+};
+struct drm_v3d_perfmon_get_values {
+  __u32 id;
+  __u32 pad;
+  __u64 values_ptr;
 };
 #ifdef __cplusplus
 }
diff --git a/libc/kernel/uapi/drm/vmwgfx_drm.h b/libc/kernel/uapi/drm/vmwgfx_drm.h
index 982b64f..f3a67e1 100644
--- a/libc/kernel/uapi/drm/vmwgfx_drm.h
+++ b/libc/kernel/uapi/drm/vmwgfx_drm.h
@@ -56,6 +56,9 @@
 #define DRM_VMW_GB_SURFACE_CREATE_EXT 27
 #define DRM_VMW_GB_SURFACE_REF_EXT 28
 #define DRM_VMW_MSG 29
+#define DRM_VMW_MKSSTAT_RESET 30
+#define DRM_VMW_MKSSTAT_ADD 31
+#define DRM_VMW_MKSSTAT_REMOVE 32
 #define DRM_VMW_PARAM_NUM_STREAMS 0
 #define DRM_VMW_PARAM_NUM_FREE_STREAMS 1
 #define DRM_VMW_PARAM_3D 2
@@ -360,6 +363,19 @@
   __s32 send_only;
   __u32 receive_len;
 };
+struct drm_vmw_mksstat_add_arg {
+  __u64 stat;
+  __u64 info;
+  __u64 strs;
+  __u64 stat_len;
+  __u64 info_len;
+  __u64 strs_len;
+  __u64 description;
+  __u64 id;
+};
+struct drm_vmw_mksstat_remove_arg {
+  __u64 id;
+};
 #ifdef __cplusplus
 }
 #endif