diff --git a/libc/kernel/uapi/misc/habanalabs.h b/libc/kernel/uapi/misc/habanalabs.h
new file mode 100644
index 0000000..c2e25de
--- /dev/null
+++ b/libc/kernel/uapi/misc/habanalabs.h
@@ -0,0 +1,193 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ***   To edit the content of this header, modify the corresponding
+ ***   source file (e.g. under external/kernel-headers/original/) then
+ ***   run bionic/libc/kernel/tools/update_all.py
+ ***
+ ***   Any manual change here will be lost the next time this script will
+ ***   be run. You've been warned!
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef HABANALABS_H_
+#define HABANALABS_H_
+#include <linux/types.h>
+#include <linux/ioctl.h>
+#define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000
+enum goya_queue_id {
+  GOYA_QUEUE_ID_DMA_0 = 0,
+  GOYA_QUEUE_ID_DMA_1,
+  GOYA_QUEUE_ID_DMA_2,
+  GOYA_QUEUE_ID_DMA_3,
+  GOYA_QUEUE_ID_DMA_4,
+  GOYA_QUEUE_ID_CPU_PQ,
+  GOYA_QUEUE_ID_MME,
+  GOYA_QUEUE_ID_TPC0,
+  GOYA_QUEUE_ID_TPC1,
+  GOYA_QUEUE_ID_TPC2,
+  GOYA_QUEUE_ID_TPC3,
+  GOYA_QUEUE_ID_TPC4,
+  GOYA_QUEUE_ID_TPC5,
+  GOYA_QUEUE_ID_TPC6,
+  GOYA_QUEUE_ID_TPC7,
+  GOYA_QUEUE_ID_SIZE
+};
+#define HL_INFO_HW_IP_INFO 0
+#define HL_INFO_HW_EVENTS 1
+#define HL_INFO_DRAM_USAGE 2
+#define HL_INFO_HW_IDLE 3
+#define HL_INFO_VERSION_MAX_LEN 128
+struct hl_info_hw_ip_info {
+  __u64 sram_base_address;
+  __u64 dram_base_address;
+  __u64 dram_size;
+  __u32 sram_size;
+  __u32 num_of_events;
+  __u32 device_id;
+  __u32 reserved[3];
+  __u32 armcp_cpld_version;
+  __u32 psoc_pci_pll_nr;
+  __u32 psoc_pci_pll_nf;
+  __u32 psoc_pci_pll_od;
+  __u32 psoc_pci_pll_div_factor;
+  __u8 tpc_enabled_mask;
+  __u8 dram_enabled;
+  __u8 pad[2];
+  __u8 armcp_version[HL_INFO_VERSION_MAX_LEN];
+};
+struct hl_info_dram_usage {
+  __u64 dram_free_mem;
+  __u64 ctx_dram_mem;
+};
+struct hl_info_hw_idle {
+  __u32 is_idle;
+  __u32 pad;
+};
+struct hl_info_args {
+  __u64 return_pointer;
+  __u32 return_size;
+  __u32 op;
+  __u32 ctx_id;
+  __u32 pad;
+};
+#define HL_CB_OP_CREATE 0
+#define HL_CB_OP_DESTROY 1
+struct hl_cb_in {
+  __u64 cb_handle;
+  __u32 op;
+  __u32 cb_size;
+  __u32 ctx_id;
+  __u32 pad;
+};
+struct hl_cb_out {
+  __u64 cb_handle;
+};
+union hl_cb_args {
+  struct hl_cb_in in;
+  struct hl_cb_out out;
+};
+struct hl_cs_chunk {
+  __u64 cb_handle;
+  __u32 queue_index;
+  __u32 cb_size;
+  __u32 cs_chunk_flags;
+  __u32 pad[11];
+};
+#define HL_CS_FLAGS_FORCE_RESTORE 0x1
+#define HL_CS_STATUS_SUCCESS 0
+struct hl_cs_in {
+  __u64 chunks_restore;
+  __u64 chunks_execute;
+  __u64 chunks_store;
+  __u32 num_chunks_restore;
+  __u32 num_chunks_execute;
+  __u32 num_chunks_store;
+  __u32 cs_flags;
+  __u32 ctx_id;
+};
+struct hl_cs_out {
+  __u64 seq;
+  __u32 status;
+  __u32 pad;
+};
+union hl_cs_args {
+  struct hl_cs_in in;
+  struct hl_cs_out out;
+};
+struct hl_wait_cs_in {
+  __u64 seq;
+  __u64 timeout_us;
+  __u32 ctx_id;
+  __u32 pad;
+};
+#define HL_WAIT_CS_STATUS_COMPLETED 0
+#define HL_WAIT_CS_STATUS_BUSY 1
+#define HL_WAIT_CS_STATUS_TIMEDOUT 2
+#define HL_WAIT_CS_STATUS_ABORTED 3
+#define HL_WAIT_CS_STATUS_INTERRUPTED 4
+struct hl_wait_cs_out {
+  __u32 status;
+  __u32 pad;
+};
+union hl_wait_cs_args {
+  struct hl_wait_cs_in in;
+  struct hl_wait_cs_out out;
+};
+#define HL_MEM_OP_ALLOC 0
+#define HL_MEM_OP_FREE 1
+#define HL_MEM_OP_MAP 2
+#define HL_MEM_OP_UNMAP 3
+#define HL_MEM_CONTIGUOUS 0x1
+#define HL_MEM_SHARED 0x2
+#define HL_MEM_USERPTR 0x4
+struct hl_mem_in {
+  union {
+    struct {
+      __u64 mem_size;
+    } alloc;
+    struct {
+      __u64 handle;
+    } free;
+    struct {
+      __u64 hint_addr;
+      __u64 handle;
+    } map_device;
+    struct {
+      __u64 host_virt_addr;
+      __u64 hint_addr;
+      __u64 mem_size;
+    } map_host;
+    struct {
+      __u64 device_virt_addr;
+    } unmap;
+  };
+  __u32 op;
+  __u32 flags;
+  __u32 ctx_id;
+  __u32 pad;
+};
+struct hl_mem_out {
+  union {
+    __u64 device_virt_addr;
+    __u64 handle;
+  };
+};
+union hl_mem_args {
+  struct hl_mem_in in;
+  struct hl_mem_out out;
+};
+#define HL_IOCTL_INFO _IOWR('H', 0x01, struct hl_info_args)
+#define HL_IOCTL_CB _IOWR('H', 0x02, union hl_cb_args)
+#define HL_IOCTL_CS _IOWR('H', 0x03, union hl_cs_args)
+#define HL_IOCTL_WAIT_CS _IOWR('H', 0x04, union hl_wait_cs_args)
+#define HL_IOCTL_MEMORY _IOWR('H', 0x05, union hl_mem_args)
+#define HL_COMMAND_START 0x01
+#define HL_COMMAND_END 0x06
+#endif