Update to v5.17 kernel headers.
Kernel headers coming from:
Git: https://android.googlesource.com/kernel/common/
Branch: android-mainline
Tag: android-mainline-5.17
Test: Boots on a flame and all bionic unit tests pass.
Change-Id: I7057d7308241f3acfa600597d287994c39ababbc
diff --git a/libc/kernel/uapi/linux/pci_regs.h b/libc/kernel/uapi/linux/pci_regs.h
index 5920633..46612da 100644
--- a/libc/kernel/uapi/linux/pci_regs.h
+++ b/libc/kernel/uapi/linux/pci_regs.h
@@ -245,21 +245,21 @@
#define PCI_SID_ESR_NSLOTS 0x1f
#define PCI_SID_ESR_FIC 0x20
#define PCI_SID_CHASSIS_NR 3
-#define PCI_MSI_FLAGS 2
+#define PCI_MSI_FLAGS 0x02
#define PCI_MSI_FLAGS_ENABLE 0x0001
#define PCI_MSI_FLAGS_QMASK 0x000e
#define PCI_MSI_FLAGS_QSIZE 0x0070
#define PCI_MSI_FLAGS_64BIT 0x0080
#define PCI_MSI_FLAGS_MASKBIT 0x0100
#define PCI_MSI_RFU 3
-#define PCI_MSI_ADDRESS_LO 4
-#define PCI_MSI_ADDRESS_HI 8
-#define PCI_MSI_DATA_32 8
-#define PCI_MSI_MASK_32 12
-#define PCI_MSI_PENDING_32 16
-#define PCI_MSI_DATA_64 12
-#define PCI_MSI_MASK_64 16
-#define PCI_MSI_PENDING_64 20
+#define PCI_MSI_ADDRESS_LO 0x04
+#define PCI_MSI_ADDRESS_HI 0x08
+#define PCI_MSI_DATA_32 0x08
+#define PCI_MSI_MASK_32 0x0c
+#define PCI_MSI_PENDING_32 0x10
+#define PCI_MSI_DATA_64 0x0c
+#define PCI_MSI_MASK_64 0x10
+#define PCI_MSI_PENDING_64 0x14
#define PCI_MSIX_FLAGS 2
#define PCI_MSIX_FLAGS_QSIZE 0x07FF
#define PCI_MSIX_FLAGS_MASKALL 0x4000
@@ -273,10 +273,10 @@
#define PCI_MSIX_FLAGS_BIRMASK PCI_MSIX_PBA_BIR
#define PCI_CAP_MSIX_SIZEOF 12
#define PCI_MSIX_ENTRY_SIZE 16
-#define PCI_MSIX_ENTRY_LOWER_ADDR 0
-#define PCI_MSIX_ENTRY_UPPER_ADDR 4
-#define PCI_MSIX_ENTRY_DATA 8
-#define PCI_MSIX_ENTRY_VECTOR_CTRL 12
+#define PCI_MSIX_ENTRY_LOWER_ADDR 0x0
+#define PCI_MSIX_ENTRY_UPPER_ADDR 0x4
+#define PCI_MSIX_ENTRY_DATA 0x8
+#define PCI_MSIX_ENTRY_VECTOR_CTRL 0xc
#define PCI_MSIX_ENTRY_CTRL_MASKBIT 0x00000001
#define PCI_CHSWP_CSR 2
#define PCI_CHSWP_DHA 0x01
@@ -379,7 +379,7 @@
#define PCI_X_BRIDGE_STATUS 4
#define PCI_SSVID_VENDOR_ID 4
#define PCI_SSVID_DEVICE_ID 6
-#define PCI_EXP_FLAGS 2
+#define PCI_EXP_FLAGS 0x02
#define PCI_EXP_FLAGS_VERS 0x000f
#define PCI_EXP_FLAGS_TYPE 0x00f0
#define PCI_EXP_TYPE_ENDPOINT 0x0
@@ -393,7 +393,7 @@
#define PCI_EXP_TYPE_RC_EC 0xa
#define PCI_EXP_FLAGS_SLOT 0x0100
#define PCI_EXP_FLAGS_IRQ 0x3e00
-#define PCI_EXP_DEVCAP 4
+#define PCI_EXP_DEVCAP 0x04
#define PCI_EXP_DEVCAP_PAYLOAD 0x00000007
#define PCI_EXP_DEVCAP_PHANTOM 0x00000018
#define PCI_EXP_DEVCAP_EXT_TAG 0x00000020
@@ -406,7 +406,7 @@
#define PCI_EXP_DEVCAP_PWR_VAL 0x03fc0000
#define PCI_EXP_DEVCAP_PWR_SCL 0x0c000000
#define PCI_EXP_DEVCAP_FLR 0x10000000
-#define PCI_EXP_DEVCTL 8
+#define PCI_EXP_DEVCTL 0x08
#define PCI_EXP_DEVCTL_CERE 0x0001
#define PCI_EXP_DEVCTL_NFERE 0x0002
#define PCI_EXP_DEVCTL_FERE 0x0004
@@ -431,7 +431,7 @@
#define PCI_EXP_DEVCTL_READRQ_2048B 0x4000
#define PCI_EXP_DEVCTL_READRQ_4096B 0x5000
#define PCI_EXP_DEVCTL_BCR_FLR 0x8000
-#define PCI_EXP_DEVSTA 10
+#define PCI_EXP_DEVSTA 0x0a
#define PCI_EXP_DEVSTA_CED 0x0001
#define PCI_EXP_DEVSTA_NFED 0x0002
#define PCI_EXP_DEVSTA_FED 0x0004
@@ -439,7 +439,7 @@
#define PCI_EXP_DEVSTA_AUXPD 0x0010
#define PCI_EXP_DEVSTA_TRPND 0x0020
#define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V1 12
-#define PCI_EXP_LNKCAP 12
+#define PCI_EXP_LNKCAP 0x0c
#define PCI_EXP_LNKCAP_SLS 0x0000000f
#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001
#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002
@@ -458,7 +458,7 @@
#define PCI_EXP_LNKCAP_DLLLARC 0x00100000
#define PCI_EXP_LNKCAP_LBNC 0x00200000
#define PCI_EXP_LNKCAP_PN 0xff000000
-#define PCI_EXP_LNKCTL 16
+#define PCI_EXP_LNKCTL 0x10
#define PCI_EXP_LNKCTL_ASPMC 0x0003
#define PCI_EXP_LNKCTL_ASPM_L0S 0x0001
#define PCI_EXP_LNKCTL_ASPM_L1 0x0002
@@ -471,7 +471,7 @@
#define PCI_EXP_LNKCTL_HAWD 0x0200
#define PCI_EXP_LNKCTL_LBMIE 0x0400
#define PCI_EXP_LNKCTL_LABIE 0x0800
-#define PCI_EXP_LNKSTA 18
+#define PCI_EXP_LNKSTA 0x12
#define PCI_EXP_LNKSTA_CLS 0x000f
#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001
#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002
@@ -491,7 +491,7 @@
#define PCI_EXP_LNKSTA_LBMS 0x4000
#define PCI_EXP_LNKSTA_LABS 0x8000
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20
-#define PCI_EXP_SLTCAP 20
+#define PCI_EXP_SLTCAP 0x14
#define PCI_EXP_SLTCAP_ABP 0x00000001
#define PCI_EXP_SLTCAP_PCP 0x00000002
#define PCI_EXP_SLTCAP_MRLSP 0x00000004
@@ -504,7 +504,7 @@
#define PCI_EXP_SLTCAP_EIP 0x00020000
#define PCI_EXP_SLTCAP_NCCS 0x00040000
#define PCI_EXP_SLTCAP_PSN 0xfff80000
-#define PCI_EXP_SLTCTL 24
+#define PCI_EXP_SLTCTL 0x18
#define PCI_EXP_SLTCTL_ABPE 0x0001
#define PCI_EXP_SLTCTL_PFDE 0x0002
#define PCI_EXP_SLTCTL_MRLSCE 0x0004
@@ -526,7 +526,7 @@
#define PCI_EXP_SLTCTL_EIC 0x0800
#define PCI_EXP_SLTCTL_DLLSCE 0x1000
#define PCI_EXP_SLTCTL_IBPD_DISABLE 0x4000
-#define PCI_EXP_SLTSTA 26
+#define PCI_EXP_SLTSTA 0x1a
#define PCI_EXP_SLTSTA_ABP 0x0001
#define PCI_EXP_SLTSTA_PFD 0x0002
#define PCI_EXP_SLTSTA_MRLSC 0x0004
@@ -536,18 +536,18 @@
#define PCI_EXP_SLTSTA_PDS 0x0040
#define PCI_EXP_SLTSTA_EIS 0x0080
#define PCI_EXP_SLTSTA_DLLSC 0x0100
-#define PCI_EXP_RTCTL 28
+#define PCI_EXP_RTCTL 0x1c
#define PCI_EXP_RTCTL_SECEE 0x0001
#define PCI_EXP_RTCTL_SENFEE 0x0002
#define PCI_EXP_RTCTL_SEFEE 0x0004
#define PCI_EXP_RTCTL_PMEIE 0x0008
#define PCI_EXP_RTCTL_CRSSVE 0x0010
-#define PCI_EXP_RTCAP 30
+#define PCI_EXP_RTCAP 0x1e
#define PCI_EXP_RTCAP_CRSVIS 0x0001
-#define PCI_EXP_RTSTA 32
+#define PCI_EXP_RTSTA 0x20
#define PCI_EXP_RTSTA_PME 0x00010000
#define PCI_EXP_RTSTA_PENDING 0x00020000
-#define PCI_EXP_DEVCAP2 36
+#define PCI_EXP_DEVCAP2 0x24
#define PCI_EXP_DEVCAP2_COMP_TMOUT_DIS 0x00000010
#define PCI_EXP_DEVCAP2_ARI 0x00000020
#define PCI_EXP_DEVCAP2_ATOMIC_ROUTE 0x00000040
@@ -559,7 +559,7 @@
#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000
#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000
#define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000
-#define PCI_EXP_DEVCTL2 40
+#define PCI_EXP_DEVCTL2 0x28
#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f
#define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS 0x0010
#define PCI_EXP_DEVCTL2_ARI 0x0020
@@ -571,9 +571,9 @@
#define PCI_EXP_DEVCTL2_OBFF_MSGA_EN 0x2000
#define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000
#define PCI_EXP_DEVCTL2_OBFF_WAKE_EN 0x6000
-#define PCI_EXP_DEVSTA2 42
-#define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2 44
-#define PCI_EXP_LNKCAP2 44
+#define PCI_EXP_DEVSTA2 0x2a
+#define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2 0x2c
+#define PCI_EXP_LNKCAP2 0x2c
#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002
#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004
#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008
@@ -581,7 +581,7 @@
#define PCI_EXP_LNKCAP2_SLS_32_0GB 0x00000020
#define PCI_EXP_LNKCAP2_SLS_64_0GB 0x00000040
#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100
-#define PCI_EXP_LNKCTL2 48
+#define PCI_EXP_LNKCTL2 0x30
#define PCI_EXP_LNKCTL2_TLS 0x000f
#define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001
#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002
@@ -592,12 +592,12 @@
#define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010
#define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380
#define PCI_EXP_LNKCTL2_HASD 0x0020
-#define PCI_EXP_LNKSTA2 50
-#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52
-#define PCI_EXP_SLTCAP2 52
+#define PCI_EXP_LNKSTA2 0x32
+#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 0x32
+#define PCI_EXP_SLTCAP2 0x34
#define PCI_EXP_SLTCAP2_IBPD 0x00000001
-#define PCI_EXP_SLTCTL2 56
-#define PCI_EXP_SLTSTA2 58
+#define PCI_EXP_SLTCTL2 0x38
+#define PCI_EXP_SLTSTA2 0x3a
#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
@@ -637,7 +637,7 @@
#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT
#define PCI_EXT_CAP_DSN_SIZEOF 12
#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
-#define PCI_ERR_UNCOR_STATUS 4
+#define PCI_ERR_UNCOR_STATUS 0x04
#define PCI_ERR_UNC_UND 0x00000001
#define PCI_ERR_UNC_DLP 0x00000010
#define PCI_ERR_UNC_SURPDN 0x00000020
@@ -655,9 +655,9 @@
#define PCI_ERR_UNC_MCBTLP 0x00800000
#define PCI_ERR_UNC_ATOMEG 0x01000000
#define PCI_ERR_UNC_TLPPRE 0x02000000
-#define PCI_ERR_UNCOR_MASK 8
-#define PCI_ERR_UNCOR_SEVER 12
-#define PCI_ERR_COR_STATUS 16
+#define PCI_ERR_UNCOR_MASK 0x08
+#define PCI_ERR_UNCOR_SEVER 0x0c
+#define PCI_ERR_COR_STATUS 0x10
#define PCI_ERR_COR_RCVR 0x00000001
#define PCI_ERR_COR_BAD_TLP 0x00000040
#define PCI_ERR_COR_BAD_DLLP 0x00000080
@@ -666,19 +666,19 @@
#define PCI_ERR_COR_ADV_NFAT 0x00002000
#define PCI_ERR_COR_INTERNAL 0x00004000
#define PCI_ERR_COR_LOG_OVER 0x00008000
-#define PCI_ERR_COR_MASK 20
-#define PCI_ERR_CAP 24
-#define PCI_ERR_CAP_FEP(x) ((x) & 31)
+#define PCI_ERR_COR_MASK 0x14
+#define PCI_ERR_CAP 0x18
+#define PCI_ERR_CAP_FEP(x) ((x) & 0x1f)
#define PCI_ERR_CAP_ECRC_GENC 0x00000020
#define PCI_ERR_CAP_ECRC_GENE 0x00000040
#define PCI_ERR_CAP_ECRC_CHKC 0x00000080
#define PCI_ERR_CAP_ECRC_CHKE 0x00000100
-#define PCI_ERR_HEADER_LOG 28
-#define PCI_ERR_ROOT_COMMAND 44
+#define PCI_ERR_HEADER_LOG 0x1c
+#define PCI_ERR_ROOT_COMMAND 0x2c
#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001
#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002
#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004
-#define PCI_ERR_ROOT_STATUS 48
+#define PCI_ERR_ROOT_STATUS 0x30
#define PCI_ERR_ROOT_COR_RCV 0x00000001
#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002
#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004
@@ -687,48 +687,48 @@
#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020
#define PCI_ERR_ROOT_FATAL_RCV 0x00000040
#define PCI_ERR_ROOT_AER_IRQ 0xf8000000
-#define PCI_ERR_ROOT_ERR_SRC 52
-#define PCI_VC_PORT_CAP1 4
+#define PCI_ERR_ROOT_ERR_SRC 0x34
+#define PCI_VC_PORT_CAP1 0x04
#define PCI_VC_CAP1_EVCC 0x00000007
#define PCI_VC_CAP1_LPEVCC 0x00000070
#define PCI_VC_CAP1_ARB_SIZE 0x00000c00
-#define PCI_VC_PORT_CAP2 8
+#define PCI_VC_PORT_CAP2 0x08
#define PCI_VC_CAP2_32_PHASE 0x00000002
#define PCI_VC_CAP2_64_PHASE 0x00000004
#define PCI_VC_CAP2_128_PHASE 0x00000008
#define PCI_VC_CAP2_ARB_OFF 0xff000000
-#define PCI_VC_PORT_CTRL 12
+#define PCI_VC_PORT_CTRL 0x0c
#define PCI_VC_PORT_CTRL_LOAD_TABLE 0x00000001
-#define PCI_VC_PORT_STATUS 14
+#define PCI_VC_PORT_STATUS 0x0e
#define PCI_VC_PORT_STATUS_TABLE 0x00000001
-#define PCI_VC_RES_CAP 16
+#define PCI_VC_RES_CAP 0x10
#define PCI_VC_RES_CAP_32_PHASE 0x00000002
#define PCI_VC_RES_CAP_64_PHASE 0x00000004
#define PCI_VC_RES_CAP_128_PHASE 0x00000008
#define PCI_VC_RES_CAP_128_PHASE_TB 0x00000010
#define PCI_VC_RES_CAP_256_PHASE 0x00000020
#define PCI_VC_RES_CAP_ARB_OFF 0xff000000
-#define PCI_VC_RES_CTRL 20
+#define PCI_VC_RES_CTRL 0x14
#define PCI_VC_RES_CTRL_LOAD_TABLE 0x00010000
#define PCI_VC_RES_CTRL_ARB_SELECT 0x000e0000
#define PCI_VC_RES_CTRL_ID 0x07000000
#define PCI_VC_RES_CTRL_ENABLE 0x80000000
-#define PCI_VC_RES_STATUS 26
+#define PCI_VC_RES_STATUS 0x1a
#define PCI_VC_RES_STATUS_TABLE 0x00000001
#define PCI_VC_RES_STATUS_NEGO 0x00000002
#define PCI_CAP_VC_BASE_SIZEOF 0x10
-#define PCI_CAP_VC_PER_VC_SIZEOF 0x0C
-#define PCI_PWR_DSR 4
-#define PCI_PWR_DATA 8
+#define PCI_CAP_VC_PER_VC_SIZEOF 0x0c
+#define PCI_PWR_DSR 0x04
+#define PCI_PWR_DATA 0x08
#define PCI_PWR_DATA_BASE(x) ((x) & 0xff)
#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3)
#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7)
#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3)
#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7)
#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7)
-#define PCI_PWR_CAP 12
+#define PCI_PWR_CAP 0x0c
#define PCI_PWR_CAP_BUDGET(x) ((x) & 1)
-#define PCI_EXT_CAP_PWR_SIZEOF 16
+#define PCI_EXT_CAP_PWR_SIZEOF 0x10
#define PCI_RCEC_RCIEP_BITMAP 4
#define PCI_RCEC_BUSN 8
#define PCI_RCEC_BUSN_REG_VER 0x02
@@ -828,7 +828,7 @@
#define PCI_SRIOV_VFM_MI 0x1
#define PCI_SRIOV_VFM_MO 0x2
#define PCI_SRIOV_VFM_AV 0x3
-#define PCI_EXT_CAP_SRIOV_SIZEOF 64
+#define PCI_EXT_CAP_SRIOV_SIZEOF 0x40
#define PCI_LTR_MAX_SNOOP_LAT 0x4
#define PCI_LTR_MAX_NOSNOOP_LAT 0x6
#define PCI_LTR_VALUE_MASK 0x000003ff
@@ -871,25 +871,25 @@
#define PCI_TPH_LOC_MSIX 0x400
#define PCI_TPH_CAP_ST_MASK 0x07FF0000
#define PCI_TPH_CAP_ST_SHIFT 16
-#define PCI_TPH_BASE_SIZEOF 12
-#define PCI_EXP_DPC_CAP 4
+#define PCI_TPH_BASE_SIZEOF 0xc
+#define PCI_EXP_DPC_CAP 0x04
#define PCI_EXP_DPC_IRQ 0x001F
#define PCI_EXP_DPC_CAP_RP_EXT 0x0020
#define PCI_EXP_DPC_CAP_POISONED_TLP 0x0040
#define PCI_EXP_DPC_CAP_SW_TRIGGER 0x0080
#define PCI_EXP_DPC_RP_PIO_LOG_SIZE 0x0F00
#define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000
-#define PCI_EXP_DPC_CTL 6
+#define PCI_EXP_DPC_CTL 0x06
#define PCI_EXP_DPC_CTL_EN_FATAL 0x0001
#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x0002
#define PCI_EXP_DPC_CTL_INT_EN 0x0008
-#define PCI_EXP_DPC_STATUS 8
+#define PCI_EXP_DPC_STATUS 0x08
#define PCI_EXP_DPC_STATUS_TRIGGER 0x0001
#define PCI_EXP_DPC_STATUS_TRIGGER_RSN 0x0006
#define PCI_EXP_DPC_STATUS_INTERRUPT 0x0008
#define PCI_EXP_DPC_RP_BUSY 0x0010
#define PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT 0x0060
-#define PCI_EXP_DPC_SOURCE_ID 10
+#define PCI_EXP_DPC_SOURCE_ID 0x0A
#define PCI_EXP_DPC_RP_PIO_STATUS 0x0C
#define PCI_EXP_DPC_RP_PIO_MASK 0x10
#define PCI_EXP_DPC_RP_PIO_SEVERITY 0x14
@@ -926,7 +926,11 @@
#define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000
#define PCI_L1SS_CTL2 0x0c
#define PCI_DVSEC_HEADER1 0x4
+#define PCI_DVSEC_HEADER1_VID(x) ((x) & 0xffff)
+#define PCI_DVSEC_HEADER1_REV(x) (((x) >> 16) & 0xf)
+#define PCI_DVSEC_HEADER1_LEN(x) (((x) >> 20) & 0xfff)
#define PCI_DVSEC_HEADER2 0x8
+#define PCI_DVSEC_HEADER2_ID(x) ((x) & 0xffff)
#define PCI_DLF_CAP 0x04
#define PCI_DLF_EXCHANGE_ENABLE 0x80000000
#define PCI_PL_16GT_LE_CTRL 0x20