commit 17a8b0db63d54e9d79bf11112ace0c4fe9606289
author Elliott Hughes <enh@google.com> Thu Mar 21 15:43:53 2013 -0700
committer Elliott Hughes <enh@google.com> Thu Mar 21 16:14:06 2013 -0700
tree 61b5f1d12776e4843e7ba70df5b20f97970be019
parent 86c318497270c80a3791b4cd9835367653636377

Expose wait4 as wait4 rather than __wait4.

This helps strace(1) compile with one fewer hack.

Change-Id: I5296d0cfec5546709cda990abd705ad33d7c4626

libc/arch-mips/syscalls/wait4.S

diff --git a/libc/arch-mips/syscalls/__wait4.S b/libc/arch-mips/syscalls/wait4.S
similarity index 81%
rename from libc/arch-mips/syscalls/__wait4.S
rename to libc/arch-mips/syscalls/wait4.S
index 713b7cb..8e3d2dc 100644
--- a/libc/arch-mips/syscalls/__wait4.S
+++ b/libc/arch-mips/syscalls/wait4.S
@@ -1,11 +1,11 @@
 /* autogenerated by gensyscalls.py */
 #include <sys/linux-syscalls.h>
     .text
-    .globl __wait4
+    .globl wait4
     .align 4
-    .ent __wait4
+    .ent wait4
 
-__wait4:
+wait4:
     .set noreorder
     .cpload $t9
     li $v0, __NR_wait4
@@ -19,4 +19,4 @@
     j $t9
     nop
     .set reorder
-    .end __wait4
+    .end wait4