Update to kernel headers v4.14.
Remove the hiding of the kernel structure binder_fd_array_object. This
structure now matches the structure used in the binder code.
Load the libclang_android.so shared library directly for parsing.
This file changed name in a recent update to the prebuilts.
Test: Compiles arm/arm64/x86/x86_64.
Test: Boots on hikey and boots on a sailfish.
Test: Ran bionic unit tests on hikey and sailfish.
Change-Id: I141a4b93ac3511cd58f4d12bb3c0d4efaa4c2742
diff --git a/libc/kernel/uapi/linux/pci_regs.h b/libc/kernel/uapi/linux/pci_regs.h
index baa9421..c7f8381 100644
--- a/libc/kernel/uapi/linux/pci_regs.h
+++ b/libc/kernel/uapi/linux/pci_regs.h
@@ -424,10 +424,12 @@
#define PCI_EXP_DEVSTA_URD 0x0008
#define PCI_EXP_DEVSTA_AUXPD 0x0010
#define PCI_EXP_DEVSTA_TRPND 0x0020
+#define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V1 12
#define PCI_EXP_LNKCAP 12
#define PCI_EXP_LNKCAP_SLS 0x0000000f
#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001
#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002
+#define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003
#define PCI_EXP_LNKCAP_MLW 0x000003f0
#define PCI_EXP_LNKCAP_ASPMS 0x00000c00
#define PCI_EXP_LNKCAP_L0SEL 0x00007000
@@ -541,7 +543,7 @@
#define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000
#define PCI_EXP_DEVCTL2_OBFF_WAKE_EN 0x6000
#define PCI_EXP_DEVSTA2 42
-#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44
+#define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2 44
#define PCI_EXP_LNKCAP2 44
#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002
#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004
@@ -549,6 +551,7 @@
#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100
#define PCI_EXP_LNKCTL2 48
#define PCI_EXP_LNKSTA2 50
+#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52
#define PCI_EXP_SLTCAP2 52
#define PCI_EXP_SLTCTL2 56
#define PCI_EXP_SLTSTA2 58
@@ -814,6 +817,7 @@
#define PCI_EXP_DPC_CAP_RP_EXT 0x20
#define PCI_EXP_DPC_CAP_POISONED_TLP 0x40
#define PCI_EXP_DPC_CAP_SW_TRIGGER 0x80
+#define PCI_EXP_DPC_RP_PIO_LOG_SIZE 0xF00
#define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000
#define PCI_EXP_DPC_CTL 6
#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x02
@@ -823,6 +827,14 @@
#define PCI_EXP_DPC_STATUS_INTERRUPT 0x08
#define PCI_EXP_DPC_RP_BUSY 0x10
#define PCI_EXP_DPC_SOURCE_ID 10
+#define PCI_EXP_DPC_RP_PIO_STATUS 0x0C
+#define PCI_EXP_DPC_RP_PIO_MASK 0x10
+#define PCI_EXP_DPC_RP_PIO_SEVERITY 0x14
+#define PCI_EXP_DPC_RP_PIO_SYSERROR 0x18
+#define PCI_EXP_DPC_RP_PIO_EXCEPTION 0x1C
+#define PCI_EXP_DPC_RP_PIO_HEADER_LOG 0x20
+#define PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG 0x30
+#define PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG 0x34
#define PCI_PTM_CAP 0x04
#define PCI_PTM_CAP_REQ 0x00000001
#define PCI_PTM_CAP_ROOT 0x00000004