diff --git a/libc/kernel/uapi/drm/amdgpu_drm.h b/libc/kernel/uapi/drm/amdgpu_drm.h
index f5e8b16..6ae9c9c 100644
--- a/libc/kernel/uapi/drm/amdgpu_drm.h
+++ b/libc/kernel/uapi/drm/amdgpu_drm.h
@@ -34,6 +34,7 @@
 #define DRM_AMDGPU_GEM_OP 0x10
 #define DRM_AMDGPU_GEM_USERPTR 0x11
 #define DRM_AMDGPU_WAIT_FENCES 0x12
+#define DRM_AMDGPU_VM 0x13
 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
@@ -47,6 +48,7 @@
 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
+#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
 #define AMDGPU_GEM_DOMAIN_CPU 0x1
 #define AMDGPU_GEM_DOMAIN_GTT 0x2
 #define AMDGPU_GEM_DOMAIN_VRAM 0x4
@@ -123,6 +125,19 @@
   struct drm_amdgpu_ctx_in in;
   union drm_amdgpu_ctx_out out;
 };
+#define AMDGPU_VM_OP_RESERVE_VMID 1
+#define AMDGPU_VM_OP_UNRESERVE_VMID 2
+struct drm_amdgpu_vm_in {
+  __u32 op;
+  __u32 flags;
+};
+struct drm_amdgpu_vm_out {
+  __u64 flags;
+};
+union drm_amdgpu_vm {
+  struct drm_amdgpu_vm_in in;
+  struct drm_amdgpu_vm_out out;
+};
 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0)
 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)
 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)
@@ -262,11 +277,15 @@
 #define AMDGPU_HW_IP_UVD 3
 #define AMDGPU_HW_IP_VCE 4
 #define AMDGPU_HW_IP_UVD_ENC 5
-#define AMDGPU_HW_IP_NUM 6
+#define AMDGPU_HW_IP_VCN_DEC 6
+#define AMDGPU_HW_IP_VCN_ENC 7
+#define AMDGPU_HW_IP_NUM 8
 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
 #define AMDGPU_CHUNK_ID_IB 0x01
 #define AMDGPU_CHUNK_ID_FENCE 0x02
 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
+#define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
+#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
 struct drm_amdgpu_cs_chunk {
   __u32 chunk_id;
   __u32 length_dw;
@@ -309,6 +328,9 @@
   __u32 handle;
   __u32 offset;
 };
+struct drm_amdgpu_cs_chunk_sem {
+  __u32 handle;
+};
 struct drm_amdgpu_cs_chunk_data {
   union {
     struct drm_amdgpu_cs_chunk_ib ib_data;
@@ -358,6 +380,7 @@
 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5
 #define AMDGPU_INFO_SENSOR_VDDNB 0x6
 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7
+#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
@@ -480,6 +503,7 @@
   __u32 gs_prim_buffer_depth;
   __u32 max_gs_waves_per_vgt;
   __u32 _pad1;
+  __u32 cu_ao_bitmap[4][4];
 };
 struct drm_amdgpu_info_hw_ip {
   __u32 hw_ip_version_major;
@@ -513,6 +537,7 @@
 #define AMDGPU_FAMILY_VI 130
 #define AMDGPU_FAMILY_CZ 135
 #define AMDGPU_FAMILY_AI 141
+#define AMDGPU_FAMILY_RV 142
 #ifdef __cplusplus
 #endif
 #endif
diff --git a/libc/kernel/uapi/drm/armada_drm.h b/libc/kernel/uapi/drm/armada_drm.h
index 331a558..ea1f37d 100644
--- a/libc/kernel/uapi/drm/armada_drm.h
+++ b/libc/kernel/uapi/drm/armada_drm.h
@@ -26,23 +26,23 @@
 #define DRM_ARMADA_GEM_PWRITE 0x03
 #define ARMADA_IOCTL(dir,name,str) DRM_ ##dir(DRM_COMMAND_BASE + DRM_ARMADA_ ##name, struct drm_armada_ ##str)
 struct drm_armada_gem_create {
-  uint32_t handle;
-  uint32_t size;
+  __u32 handle;
+  __u32 size;
 };
 #define DRM_IOCTL_ARMADA_GEM_CREATE ARMADA_IOCTL(IOWR, GEM_CREATE, gem_create)
 struct drm_armada_gem_mmap {
-  uint32_t handle;
-  uint32_t pad;
-  uint64_t offset;
-  uint64_t size;
-  uint64_t addr;
+  __u32 handle;
+  __u32 pad;
+  __u64 offset;
+  __u64 size;
+  __u64 addr;
 };
 #define DRM_IOCTL_ARMADA_GEM_MMAP ARMADA_IOCTL(IOWR, GEM_MMAP, gem_mmap)
 struct drm_armada_gem_pwrite {
-  uint64_t ptr;
-  uint32_t handle;
-  uint32_t offset;
-  uint32_t size;
+  __u64 ptr;
+  __u32 handle;
+  __u32 offset;
+  __u32 size;
 };
 #define DRM_IOCTL_ARMADA_GEM_PWRITE ARMADA_IOCTL(IOW, GEM_PWRITE, gem_pwrite)
 #ifdef __cplusplus
diff --git a/libc/kernel/uapi/drm/drm.h b/libc/kernel/uapi/drm/drm.h
index 251deeb..6863dc1 100644
--- a/libc/kernel/uapi/drm/drm.h
+++ b/libc/kernel/uapi/drm/drm.h
@@ -361,6 +361,7 @@
 #define DRM_CAP_ADDFB2_MODIFIERS 0x10
 #define DRM_CAP_PAGE_FLIP_TARGET 0x11
 #define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12
+#define DRM_CAP_SYNCOBJ 0x13
 struct drm_get_cap {
   __u64 capability;
   __u64 value;
@@ -379,6 +380,38 @@
   __u32 flags;
   __s32 fd;
 };
+struct drm_syncobj_create {
+  __u32 handle;
+#define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0)
+  __u32 flags;
+};
+struct drm_syncobj_destroy {
+  __u32 handle;
+  __u32 pad;
+};
+#define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0)
+#define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0)
+struct drm_syncobj_handle {
+  __u32 handle;
+  __u32 flags;
+  __s32 fd;
+  __u32 pad;
+};
+#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)
+#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
+struct drm_syncobj_wait {
+  __u64 handles;
+  __s64 timeout_nsec;
+  __u32 count_handles;
+  __u32 flags;
+  __u32 first_signaled;
+  __u32 pad;
+};
+struct drm_syncobj_array {
+  __u64 handles;
+  __u32 count_handles;
+  __u32 pad;
+};
 #ifdef __cplusplus
 #endif
 #include "drm_mode.h"
@@ -477,6 +510,13 @@
 #define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic)
 #define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob)
 #define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob)
+#define DRM_IOCTL_SYNCOBJ_CREATE DRM_IOWR(0xBF, struct drm_syncobj_create)
+#define DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct drm_syncobj_destroy)
+#define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD DRM_IOWR(0xC1, struct drm_syncobj_handle)
+#define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE DRM_IOWR(0xC2, struct drm_syncobj_handle)
+#define DRM_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct drm_syncobj_wait)
+#define DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct drm_syncobj_array)
+#define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array)
 #define DRM_COMMAND_BASE 0x40
 #define DRM_COMMAND_END 0xA0
 struct drm_event {
diff --git a/libc/kernel/uapi/drm/drm_fourcc.h b/libc/kernel/uapi/drm/drm_fourcc.h
index 630ad30..da416cf 100644
--- a/libc/kernel/uapi/drm/drm_fourcc.h
+++ b/libc/kernel/uapi/drm/drm_fourcc.h
@@ -105,11 +105,16 @@
 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
+#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
+#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
 #define fourcc_mod_code(vendor,val) ((((__u64) DRM_FORMAT_MOD_VENDOR_ ##vendor) << 56) | (val & 0x00ffffffffffffffULL))
+#define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
+#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
+#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
@@ -121,6 +126,7 @@
 #define fourcc_mod_tegra_param(m) (m & ((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
 #define NV_FORMAT_MOD_TEGRA_TILED fourcc_mod_tegra_code(1, 0)
 #define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v)
+#define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
 #ifdef __cplusplus
 #endif
 #endif
diff --git a/libc/kernel/uapi/drm/drm_mode.h b/libc/kernel/uapi/drm/drm_mode.h
index 9e7ee92..5e97a72 100644
--- a/libc/kernel/uapi/drm/drm_mode.h
+++ b/libc/kernel/uapi/drm/drm_mode.h
@@ -79,6 +79,14 @@
 #define DRM_MODE_DIRTY_ANNOTATE 2
 #define DRM_MODE_LINK_STATUS_GOOD 0
 #define DRM_MODE_LINK_STATUS_BAD 1
+#define DRM_MODE_ROTATE_0 (1 << 0)
+#define DRM_MODE_ROTATE_90 (1 << 1)
+#define DRM_MODE_ROTATE_180 (1 << 2)
+#define DRM_MODE_ROTATE_270 (1 << 3)
+#define DRM_MODE_ROTATE_MASK (DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270)
+#define DRM_MODE_REFLECT_X (1 << 4)
+#define DRM_MODE_REFLECT_Y (1 << 5)
+#define DRM_MODE_REFLECT_MASK (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y)
 struct drm_mode_modeinfo {
   __u32 clock;
   __u16 hdisplay;
@@ -396,6 +404,21 @@
   __u64 reserved;
   __u64 user_data;
 };
+struct drm_format_modifier_blob {
+#define FORMAT_BLOB_CURRENT 1
+  __u32 version;
+  __u32 flags;
+  __u32 count_formats;
+  __u32 formats_offset;
+  __u32 count_modifiers;
+  __u32 modifiers_offset;
+};
+struct drm_format_modifier {
+  __u64 formats;
+  __u32 offset;
+  __u32 pad;
+  __u64 modifier;
+};
 struct drm_mode_create_blob {
   __u64 data;
   __u32 length;
diff --git a/libc/kernel/uapi/drm/i915_drm.h b/libc/kernel/uapi/drm/i915_drm.h
index af6f064..50ea43a 100644
--- a/libc/kernel/uapi/drm/i915_drm.h
+++ b/libc/kernel/uapi/drm/i915_drm.h
@@ -172,6 +172,8 @@
 #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
 #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
 #define DRM_I915_PERF_OPEN 0x36
+#define DRM_I915_PERF_ADD_CONFIG 0x37
+#define DRM_I915_PERF_REMOVE_CONFIG 0x38
 #define DRM_IOCTL_I915_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLUSH)
 #define DRM_IOCTL_I915_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLIP)
@@ -226,6 +228,8 @@
 #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
 #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
 #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
+#define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
+#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
 typedef struct drm_i915_batchbuffer {
   int start;
   int used;
@@ -292,6 +296,11 @@
 #define I915_PARAM_HUC_STATUS 42
 #define I915_PARAM_HAS_EXEC_ASYNC 43
 #define I915_PARAM_HAS_EXEC_FENCE 44
+#define I915_PARAM_HAS_EXEC_CAPTURE 45
+#define I915_PARAM_SLICE_MASK 46
+#define I915_PARAM_SUBSLICE_MASK 47
+#define I915_PARAM_HAS_EXEC_BATCH_FIRST 48
+#define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49
 typedef struct drm_i915_getparam {
   __s32 param;
   int __user * value;
@@ -396,6 +405,7 @@
 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
 #define I915_GEM_DOMAIN_VERTEX 0x00000020
 #define I915_GEM_DOMAIN_GTT 0x00000040
+#define I915_GEM_DOMAIN_WC 0x00000080
 struct drm_i915_gem_exec_object {
   __u32 handle;
   __u32 relocation_count;
@@ -426,7 +436,8 @@
 #define EXEC_OBJECT_PINNED (1 << 4)
 #define EXEC_OBJECT_PAD_TO_SIZE (1 << 5)
 #define EXEC_OBJECT_ASYNC (1 << 6)
-#define __EXEC_OBJECT_UNKNOWN_FLAGS - (EXEC_OBJECT_ASYNC << 1)
+#define EXEC_OBJECT_CAPTURE (1 << 7)
+#define __EXEC_OBJECT_UNKNOWN_FLAGS - (EXEC_OBJECT_CAPTURE << 1)
   __u64 flags;
   union {
     __u64 rsvd1;
@@ -434,6 +445,13 @@
   };
   __u64 rsvd2;
 };
+struct drm_i915_gem_exec_fence {
+  __u32 handle;
+#define I915_EXEC_FENCE_WAIT (1 << 0)
+#define I915_EXEC_FENCE_SIGNAL (1 << 1)
+#define __I915_EXEC_FENCE_UNKNOWN_FLAGS (- (I915_EXEC_FENCE_SIGNAL << 1))
+  __u32 flags;
+};
 struct drm_i915_gem_execbuffer2 {
   __u64 buffers_ptr;
   __u32 buffer_count;
@@ -470,7 +488,9 @@
 #define I915_EXEC_RESOURCE_STREAMER (1 << 15)
 #define I915_EXEC_FENCE_IN (1 << 16)
 #define I915_EXEC_FENCE_OUT (1 << 17)
-#define __I915_EXEC_UNKNOWN_FLAGS (- (I915_EXEC_FENCE_OUT << 1))
+#define I915_EXEC_BATCH_FIRST (1 << 18)
+#define I915_EXEC_FENCE_ARRAY (1 << 19)
+#define __I915_EXEC_UNKNOWN_FLAGS (- (I915_EXEC_FENCE_ARRAY << 1))
 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
 #define i915_execbuffer2_set_context_id(eb2,context) (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
 #define i915_execbuffer2_get_context_id(eb2) ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
@@ -650,6 +670,9 @@
   I915_OA_FORMAT_A45_B8_C8,
   I915_OA_FORMAT_B4_C8_A16,
   I915_OA_FORMAT_C4_B8,
+  I915_OA_FORMAT_A12,
+  I915_OA_FORMAT_A12_B8_C8,
+  I915_OA_FORMAT_A32u40_A4u32_B8_C8,
   I915_OA_FORMAT_MAX
 };
 enum drm_i915_perf_property_id {
@@ -681,6 +704,15 @@
   DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3,
   DRM_I915_PERF_RECORD_MAX
 };
+struct drm_i915_perf_oa_config {
+  char uuid[36];
+  __u32 n_mux_regs;
+  __u32 n_boolean_regs;
+  __u32 n_flex_regs;
+  __u64 __user mux_regs_ptr;
+  __u64 __user boolean_regs_ptr;
+  __u64 __user flex_regs_ptr;
+};
 #ifdef __cplusplus
 #endif
 #endif
diff --git a/libc/kernel/uapi/drm/msm_drm.h b/libc/kernel/uapi/drm/msm_drm.h
index 83ad769..4f1a423 100644
--- a/libc/kernel/uapi/drm/msm_drm.h
+++ b/libc/kernel/uapi/drm/msm_drm.h
@@ -55,9 +55,11 @@
   __u32 flags;
   __u32 handle;
 };
+#define MSM_INFO_IOVA 0x01
+#define MSM_INFO_FLAGS (MSM_INFO_IOVA)
 struct drm_msm_gem_info {
   __u32 handle;
-  __u32 pad;
+  __u32 flags;
   __u64 offset;
 };
 #define MSM_PREP_READ 0x01
@@ -89,7 +91,7 @@
   __u32 size;
   __u32 pad;
   __u32 nr_relocs;
-  __u64 __user relocs;
+  __u64 relocs;
 };
 #define MSM_SUBMIT_BO_READ 0x0001
 #define MSM_SUBMIT_BO_WRITE 0x0002
@@ -108,8 +110,8 @@
   __u32 fence;
   __u32 nr_bos;
   __u32 nr_cmds;
-  __u64 __user bos;
-  __u64 __user cmds;
+  __u64 bos;
+  __u64 cmds;
   __s32 fence_fd;
 };
 struct drm_msm_wait_fence {
@@ -133,7 +135,6 @@
 #define DRM_MSM_GEM_SUBMIT 0x06
 #define DRM_MSM_WAIT_FENCE 0x07
 #define DRM_MSM_GEM_MADVISE 0x08
-#define DRM_MSM_NUM_IOCTLS 0x09
 #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
 #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
 #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
diff --git a/libc/kernel/uapi/drm/qxl_drm.h b/libc/kernel/uapi/drm/qxl_drm.h
index c1966ae..5942635 100644
--- a/libc/kernel/uapi/drm/qxl_drm.h
+++ b/libc/kernel/uapi/drm/qxl_drm.h
@@ -51,8 +51,8 @@
   __u32 pad;
 };
 struct drm_qxl_command {
-  __u64 __user command;
-  __u64 __user relocs;
+  __u64 command;
+  __u64 relocs;
   __u32 type;
   __u32 command_size;
   __u32 relocs_num;
@@ -61,7 +61,7 @@
 struct drm_qxl_execbuffer {
   __u32 flags;
   __u32 commands_num;
-  __u64 __user commands;
+  __u64 commands;
 };
 struct drm_qxl_update_area {
   __u32 handle;
diff --git a/libc/kernel/uapi/drm/vc4_drm.h b/libc/kernel/uapi/drm/vc4_drm.h
index 8c59253..d96c49d 100644
--- a/libc/kernel/uapi/drm/vc4_drm.h
+++ b/libc/kernel/uapi/drm/vc4_drm.h
@@ -29,6 +29,9 @@
 #define DRM_VC4_CREATE_SHADER_BO 0x05
 #define DRM_VC4_GET_HANG_STATE 0x06
 #define DRM_VC4_GET_PARAM 0x07
+#define DRM_VC4_SET_TILING 0x08
+#define DRM_VC4_GET_TILING 0x09
+#define DRM_VC4_LABEL_BO 0x0a
 #define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
 #define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
 #define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)
@@ -37,6 +40,9 @@
 #define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
 #define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)
 #define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param)
+#define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling)
+#define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling)
+#define DRM_IOCTL_VC4_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo)
 struct drm_vc4_submit_rcl_surface {
   __u32 hindex;
   __u32 offset;
@@ -71,6 +77,9 @@
   __u8 clear_s;
   __u32 pad : 24;
 #define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0)
+#define VC4_SUBMIT_CL_FIXED_RCL_ORDER (1 << 1)
+#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X (1 << 2)
+#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y (1 << 3)
   __u32 flags;
   __u64 seqno;
 };
@@ -132,11 +141,27 @@
 #define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3
 #define DRM_VC4_PARAM_SUPPORTS_ETC1 4
 #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5
+#define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER 6
 struct drm_vc4_get_param {
   __u32 param;
   __u32 pad;
   __u64 value;
 };
+struct drm_vc4_get_tiling {
+  __u32 handle;
+  __u32 flags;
+  __u64 modifier;
+};
+struct drm_vc4_set_tiling {
+  __u32 handle;
+  __u32 flags;
+  __u64 modifier;
+};
+struct drm_vc4_label_bo {
+  __u32 handle;
+  __u32 len;
+  __u64 name;
+};
 #ifdef __cplusplus
 #endif
 #endif
diff --git a/libc/kernel/uapi/drm/vmwgfx_drm.h b/libc/kernel/uapi/drm/vmwgfx_drm.h
index 2b7e0fe..f6a7b14 100644
--- a/libc/kernel/uapi/drm/vmwgfx_drm.h
+++ b/libc/kernel/uapi/drm/vmwgfx_drm.h
@@ -104,6 +104,8 @@
   struct drm_vmw_surface_arg req;
 };
 #define DRM_VMW_EXECBUF_VERSION 2
+#define DRM_VMW_EXECBUF_FLAG_IMPORT_FENCE_FD (1 << 0)
+#define DRM_VMW_EXECBUF_FLAG_EXPORT_FENCE_FD (1 << 1)
 struct drm_vmw_execbuf_arg {
   __u64 commands;
   __u32 command_size;
@@ -112,14 +114,14 @@
   __u32 version;
   __u32 flags;
   __u32 context_handle;
-  __u32 pad64;
+  __s32 imported_fence_fd;
 };
 struct drm_vmw_fence_rep {
   __u32 handle;
   __u32 mask;
   __u32 seqno;
   __u32 passed_seqno;
-  __u32 pad64;
+  __s32 fd;
   __s32 error;
 };
 struct drm_vmw_alloc_dmabuf_req {