diff --git a/libc/kernel/uapi/drm/amdgpu_drm.h b/libc/kernel/uapi/drm/amdgpu_drm.h
index aa3f30f..1e5b8e3 100644
--- a/libc/kernel/uapi/drm/amdgpu_drm.h
+++ b/libc/kernel/uapi/drm/amdgpu_drm.h
@@ -64,6 +64,7 @@
 #define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12)
 #define AMDGPU_GEM_CREATE_COHERENT (1 << 13)
 #define AMDGPU_GEM_CREATE_UNCACHED (1 << 14)
+#define AMDGPU_GEM_CREATE_EXT_COHERENT (1 << 15)
 struct drm_amdgpu_gem_create_in {
   __u64 bo_size;
   __u64 alignment;
@@ -331,7 +332,8 @@
 #define AMDGPU_HW_IP_VCN_DEC 6
 #define AMDGPU_HW_IP_VCN_ENC 7
 #define AMDGPU_HW_IP_VCN_JPEG 8
-#define AMDGPU_HW_IP_NUM 9
+#define AMDGPU_HW_IP_VPE 9
+#define AMDGPU_HW_IP_NUM 10
 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
 #define AMDGPU_CHUNK_ID_IB 0x01
 #define AMDGPU_CHUNK_ID_FENCE 0x02
@@ -459,6 +461,7 @@
 #define AMDGPU_INFO_FW_MES_KIQ 0x19
 #define AMDGPU_INFO_FW_MES 0x1a
 #define AMDGPU_INFO_FW_IMU 0x1b
+#define AMDGPU_INFO_FW_VPE 0x1c
 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
 #define AMDGPU_INFO_VRAM_USAGE 0x10
 #define AMDGPU_INFO_GTT_USAGE 0x11
@@ -508,6 +511,7 @@
 #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0
 #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1
 #define AMDGPU_INFO_MAX_IBS 0x22
+#define AMDGPU_INFO_GPUVM_FAULT 0x23
 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
@@ -711,6 +715,18 @@
 struct drm_amdgpu_info_video_caps {
   struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT];
 };
+#define AMDGPU_VMHUB_TYPE_MASK 0xff
+#define AMDGPU_VMHUB_TYPE_SHIFT 0
+#define AMDGPU_VMHUB_TYPE_GFX 0
+#define AMDGPU_VMHUB_TYPE_MM0 1
+#define AMDGPU_VMHUB_TYPE_MM1 2
+#define AMDGPU_VMHUB_IDX_MASK 0xff00
+#define AMDGPU_VMHUB_IDX_SHIFT 8
+struct drm_amdgpu_info_gpuvm_fault {
+  __u64 addr;
+  __u32 status;
+  __u32 vmhub;
+};
 #define AMDGPU_FAMILY_UNKNOWN 0
 #define AMDGPU_FAMILY_SI 110
 #define AMDGPU_FAMILY_CI 120
@@ -726,6 +742,7 @@
 #define AMDGPU_FAMILY_GC_11_0_1 148
 #define AMDGPU_FAMILY_GC_10_3_6 149
 #define AMDGPU_FAMILY_GC_10_3_7 151
+#define AMDGPU_FAMILY_GC_11_5_0 150
 #ifdef __cplusplus
 }
 #endif
diff --git a/libc/kernel/uapi/drm/drm_fourcc.h b/libc/kernel/uapi/drm/drm_fourcc.h
index 8190325..6fd2eb8 100644
--- a/libc/kernel/uapi/drm/drm_fourcc.h
+++ b/libc/kernel/uapi/drm/drm_fourcc.h
@@ -119,6 +119,8 @@
 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4')
 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2')
 #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5')
+#define DRM_FORMAT_NV20 fourcc_code('N', 'V', '2', '0')
+#define DRM_FORMAT_NV30 fourcc_code('N', 'V', '3', '0')
 #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0')
 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0')
 #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2')
diff --git a/libc/kernel/uapi/drm/habanalabs_accel.h b/libc/kernel/uapi/drm/habanalabs_accel.h
index 44fd8c8..158e937 100644
--- a/libc/kernel/uapi/drm/habanalabs_accel.h
+++ b/libc/kernel/uapi/drm/habanalabs_accel.h
@@ -6,8 +6,7 @@
  */
 #ifndef HABANALABS_H_
 #define HABANALABS_H_
-#include <linux/types.h>
-#include <linux/ioctl.h>
+#include <drm/drm.h>
 #define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000
 #define GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START 0x80
 #define GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT 144
@@ -656,6 +655,7 @@
 #define HL_INFO_FW_GENERIC_REQ 35
 #define HL_INFO_HW_ERR_EVENT 36
 #define HL_INFO_FW_ERR_EVENT 37
+#define HL_INFO_USER_ENGINE_ERR_EVENT 38
 #define HL_INFO_VERSION_MAX_LEN 128
 #define HL_INFO_CARD_NAME_MAX_LEN 16
 #define HL_ENGINES_DATA_MAX_SIZE SZ_1M
@@ -729,6 +729,7 @@
 struct hl_info_time_sync {
   __u64 device_time;
   __u64 host_time;
+  __u64 tsc_time;
 };
 struct hl_info_pci_counters {
   __u64 rx_throughput;
@@ -834,6 +835,12 @@
   __u16 event_id;
   __u32 pad;
 };
+struct hl_info_engine_err_event {
+  __s64 timestamp;
+  __u16 engine_id;
+  __u16 error_count;
+  __u32 pad;
+};
 struct hl_info_dev_memalloc_page_sizes {
   __u64 page_order_bitmask;
 };
@@ -1183,12 +1190,18 @@
   __u32 enable;
   __u32 ctx_id;
 };
-#define HL_IOCTL_INFO _IOWR('H', 0x01, struct hl_info_args)
-#define HL_IOCTL_CB _IOWR('H', 0x02, union hl_cb_args)
-#define HL_IOCTL_CS _IOWR('H', 0x03, union hl_cs_args)
-#define HL_IOCTL_WAIT_CS _IOWR('H', 0x04, union hl_wait_cs_args)
-#define HL_IOCTL_MEMORY _IOWR('H', 0x05, union hl_mem_args)
-#define HL_IOCTL_DEBUG _IOWR('H', 0x06, struct hl_debug_args)
-#define HL_COMMAND_START 0x01
-#define HL_COMMAND_END 0x07
+#define HL_IOCTL_INFO 0x00
+#define HL_IOCTL_CB 0x01
+#define HL_IOCTL_CS 0x02
+#define HL_IOCTL_WAIT_CS 0x03
+#define HL_IOCTL_MEMORY 0x04
+#define HL_IOCTL_DEBUG 0x05
+#define DRM_IOCTL_HL_INFO DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_INFO, struct hl_info_args)
+#define DRM_IOCTL_HL_CB DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_CB, union hl_cb_args)
+#define DRM_IOCTL_HL_CS DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_CS, union hl_cs_args)
+#define DRM_IOCTL_HL_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_WAIT_CS, union hl_wait_cs_args)
+#define DRM_IOCTL_HL_MEMORY DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_MEMORY, union hl_mem_args)
+#define DRM_IOCTL_HL_DEBUG DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_DEBUG, struct hl_debug_args)
+#define HL_COMMAND_START (DRM_COMMAND_BASE + HL_IOCTL_INFO)
+#define HL_COMMAND_END (DRM_COMMAND_BASE + HL_IOCTL_DEBUG + 1)
 #endif
diff --git a/libc/kernel/uapi/drm/qaic_accel.h b/libc/kernel/uapi/drm/qaic_accel.h
index 3e6bb2a..9e50aec 100644
--- a/libc/kernel/uapi/drm/qaic_accel.h
+++ b/libc/kernel/uapi/drm/qaic_accel.h
@@ -170,6 +170,10 @@
   __u32 device_latency_us;
   __u32 pad;
 };
+struct qaic_detach_slice {
+  __u32 handle;
+  __u32 pad;
+};
 #define DRM_QAIC_MANAGE 0x00
 #define DRM_QAIC_CREATE_BO 0x01
 #define DRM_QAIC_MMAP_BO 0x02
@@ -178,6 +182,7 @@
 #define DRM_QAIC_PARTIAL_EXECUTE_BO 0x05
 #define DRM_QAIC_WAIT_BO 0x06
 #define DRM_QAIC_PERF_STATS_BO 0x07
+#define DRM_QAIC_DETACH_SLICE_BO 0x08
 #define DRM_IOCTL_QAIC_MANAGE DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_MANAGE, struct qaic_manage_msg)
 #define DRM_IOCTL_QAIC_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_CREATE_BO, struct qaic_create_bo)
 #define DRM_IOCTL_QAIC_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_MMAP_BO, struct qaic_mmap_bo)
@@ -186,6 +191,7 @@
 #define DRM_IOCTL_QAIC_PARTIAL_EXECUTE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_PARTIAL_EXECUTE_BO, struct qaic_execute)
 #define DRM_IOCTL_QAIC_WAIT_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_WAIT_BO, struct qaic_wait)
 #define DRM_IOCTL_QAIC_PERF_STATS_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_PERF_STATS_BO, struct qaic_perf_stats)
+#define DRM_IOCTL_QAIC_DETACH_SLICE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_DETACH_SLICE_BO, struct qaic_detach_slice)
 #ifdef __cplusplus
 }
 #endif