diff --git a/libc/kernel/uapi/asm-riscv/asm/elf.h b/libc/kernel/uapi/asm-riscv/asm/elf.h
index 11abe46..df15148 100644
--- a/libc/kernel/uapi/asm-riscv/asm/elf.h
+++ b/libc/kernel/uapi/asm-riscv/asm/elf.h
@@ -32,6 +32,7 @@
 #define R_RISCV_TLS_DTPREL64 9
 #define R_RISCV_TLS_TPREL32 10
 #define R_RISCV_TLS_TPREL64 11
+#define R_RISCV_IRELATIVE 58
 #define R_RISCV_BRANCH 16
 #define R_RISCV_JAL 17
 #define R_RISCV_CALL 18
@@ -62,7 +63,6 @@
 #define R_RISCV_ALIGN 43
 #define R_RISCV_RVC_BRANCH 44
 #define R_RISCV_RVC_JUMP 45
-#define R_RISCV_LUI 46
 #define R_RISCV_GPREL_I 47
 #define R_RISCV_GPREL_S 48
 #define R_RISCV_TPREL_I 49
@@ -74,4 +74,7 @@
 #define R_RISCV_SET16 55
 #define R_RISCV_SET32 56
 #define R_RISCV_32_PCREL 57
+#define R_RISCV_PLT32 59
+#define R_RISCV_SET_ULEB128 60
+#define R_RISCV_SUB_ULEB128 61
 #endif
diff --git a/libc/kernel/uapi/asm-riscv/asm/hwprobe.h b/libc/kernel/uapi/asm-riscv/asm/hwprobe.h
index 7571e3f..a18b020 100644
--- a/libc/kernel/uapi/asm-riscv/asm/hwprobe.h
+++ b/libc/kernel/uapi/asm-riscv/asm/hwprobe.h
@@ -23,6 +23,7 @@
 #define RISCV_HWPROBE_EXT_ZBA (1 << 3)
 #define RISCV_HWPROBE_EXT_ZBB (1 << 4)
 #define RISCV_HWPROBE_EXT_ZBS (1 << 5)
+#define RISCV_HWPROBE_EXT_ZICBOZ (1 << 6)
 #define RISCV_HWPROBE_KEY_CPUPERF_0 5
 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
 #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
@@ -30,4 +31,5 @@
 #define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0)
 #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0)
 #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0)
+#define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6
 #endif
diff --git a/libc/kernel/uapi/asm-riscv/asm/kvm.h b/libc/kernel/uapi/asm-riscv/asm/kvm.h
index 2a3424e..470d581 100644
--- a/libc/kernel/uapi/asm-riscv/asm/kvm.h
+++ b/libc/kernel/uapi/asm-riscv/asm/kvm.h
@@ -53,6 +53,7 @@
   unsigned long sip;
   unsigned long satp;
   unsigned long scounteren;
+  unsigned long senvcfg;
 };
 struct kvm_riscv_aia_csr {
   unsigned long siselect;
@@ -63,6 +64,9 @@
   unsigned long iprio1h;
   unsigned long iprio2h;
 };
+struct kvm_riscv_smstateen_csr {
+  unsigned long sstateen0;
+};
 struct kvm_riscv_timer {
   __u64 frequency;
   __u64 time;
@@ -93,6 +97,8 @@
   KVM_RISCV_ISA_EXT_ZICSR,
   KVM_RISCV_ISA_EXT_ZIFENCEI,
   KVM_RISCV_ISA_EXT_ZIHPM,
+  KVM_RISCV_ISA_EXT_SMSTATEEN,
+  KVM_RISCV_ISA_EXT_ZICOND,
   KVM_RISCV_ISA_EXT_MAX,
 };
 enum KVM_RISCV_SBI_EXT_ID {
@@ -105,6 +111,7 @@
   KVM_RISCV_SBI_EXT_PMU,
   KVM_RISCV_SBI_EXT_EXPERIMENTAL,
   KVM_RISCV_SBI_EXT_VENDOR,
+  KVM_RISCV_SBI_EXT_DBCN,
   KVM_RISCV_SBI_EXT_MAX,
 };
 #define KVM_RISCV_TIMER_STATE_OFF 0
@@ -121,8 +128,10 @@
 #define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT)
 #define KVM_REG_RISCV_CSR_GENERAL (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
 #define KVM_REG_RISCV_CSR_AIA (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
+#define KVM_REG_RISCV_CSR_SMSTATEEN (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT)
 #define KVM_REG_RISCV_CSR_REG(name) (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))
 #define KVM_REG_RISCV_CSR_AIA_REG(name) (offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long))
+#define KVM_REG_RISCV_CSR_SMSTATEEN_REG(name) (offsetof(struct kvm_riscv_smstateen_csr, name) / sizeof(unsigned long))
 #define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT)
 #define KVM_REG_RISCV_TIMER_REG(name) (offsetof(struct kvm_riscv_timer, name) / sizeof(__u64))
 #define KVM_REG_RISCV_FP_F (0x05 << KVM_REG_RISCV_TYPE_SHIFT)