diff --git a/libc/arch-riscv64/bionic/__bionic_clone.S b/libc/arch-riscv64/bionic/__bionic_clone.S
index aeb2da6..d535095 100644
--- a/libc/arch-riscv64/bionic/__bionic_clone.S
+++ b/libc/arch-riscv64/bionic/__bionic_clone.S
@@ -34,7 +34,7 @@
   # Push 'fn' and 'arg' onto the child stack.
   addi a1, a1, -16
   sd a5, 0(a1)
-  sd a6, 0(a1)
+  sd a6, 8(a1)
 
   # Make the system call.
   li a7, __NR_clone
diff --git a/libc/arch-riscv64/bionic/setjmp.S b/libc/arch-riscv64/bionic/setjmp.S
index 812cfd1..2811bbe 100644
--- a/libc/arch-riscv64/bionic/setjmp.S
+++ b/libc/arch-riscv64/bionic/setjmp.S
@@ -141,16 +141,14 @@
   addi a2, a0, _JB_SIGMASK // old_mask.
   call PIC_PLT(sigprocmask)
 
-  ld a1, 8(sp)
-
 1:
-  // Restore original a0/a1/ra.
+  // Restore original a0/ra.
   ld a0, 0(sp)
-  ld a1, 8(sp)
   ld ra, 16(sp)
   addi sp, sp, 24
 
-  // Mask off the signal flag bit.
+  // Get the cookie.
+  ld a1, _JB_SIGFLAG(a0)
   andi a1, a1, -2
 
   // Save core registers.
@@ -169,7 +167,7 @@
   sd s9,  _JB_S9(a0)
   sd s10, _JB_S10(a0)
   sd s11, _JB_S11(a0)
-  sd sp,  _JB_SP(a0)
+  sd a2,  _JB_SP(a0)
   m_unmangle_registers a1, sp_reg=a2
 
   // Save floating point registers.
diff --git a/libm/arm64/fenv.c b/libm/arm64/fenv.c
index a99288b..369140b 100644
--- a/libm/arm64/fenv.c
+++ b/libm/arm64/fenv.c
@@ -59,7 +59,6 @@
 
 int fesetenv(const fenv_t* envp) {
   fpu_control_t fpcr;
-
   __get_fpcr(fpcr);
   if (envp->__control != fpcr) {
     __set_fpcr(envp->__control);
@@ -70,27 +69,22 @@
 
 int feclearexcept(int excepts) {
   fpu_status_t fpsr;
-
-  excepts &= FE_ALL_EXCEPT;
   __get_fpsr(fpsr);
-  fpsr &= ~excepts;
+  fpsr &= ~(excepts & FE_ALL_EXCEPT);
   __set_fpsr(fpsr);
   return 0;
 }
 
 int fegetexceptflag(fexcept_t* flagp, int excepts) {
   fpu_status_t fpsr;
-
-  excepts &= FE_ALL_EXCEPT;
   __get_fpsr(fpsr);
-  *flagp = fpsr & excepts;
+  *flagp = fpsr & (excepts & FE_ALL_EXCEPT);
   return 0;
 }
 
 int fesetexceptflag(const fexcept_t* flagp, int excepts) {
-  fpu_status_t fpsr;
-
   excepts &= FE_ALL_EXCEPT;
+  fpu_status_t fpsr;
   __get_fpsr(fpsr);
   fpsr &= ~excepts;
   fpsr |= *flagp & excepts;
@@ -100,32 +94,27 @@
 
 int feraiseexcept(int excepts) {
   fexcept_t ex = excepts;
-
   fesetexceptflag(&ex, excepts);
   return 0;
 }
 
 int fetestexcept(int excepts) {
   fpu_status_t fpsr;
-
-  excepts &= FE_ALL_EXCEPT;
   __get_fpsr(fpsr);
-  return (fpsr & excepts);
+  return (fpsr & (excepts & FE_ALL_EXCEPT));
 }
 
 int fegetround(void) {
   fpu_control_t fpcr;
-
   __get_fpcr(fpcr);
   return ((fpcr >> FPCR_RMODE_SHIFT) & FE_TOWARDZERO);
 }
 
 int fesetround(int round) {
-  fpu_control_t fpcr, new_fpcr;
-
-  round &= FE_TOWARDZERO;
+  if (round < FE_TONEAREST || round > FE_UPWARD) return -1;
+  fpu_control_t fpcr;
   __get_fpcr(fpcr);
-  new_fpcr = fpcr & ~(FE_TOWARDZERO << FPCR_RMODE_SHIFT);
+  fpu_control_t new_fpcr = fpcr & ~(FE_TOWARDZERO << FPCR_RMODE_SHIFT);
   new_fpcr |= (round << FPCR_RMODE_SHIFT);
   if (new_fpcr != fpcr) {
     __set_fpcr(new_fpcr);
@@ -134,33 +123,15 @@
 }
 
 int feholdexcept(fenv_t* envp) {
-  fpu_status_t fpsr;
-  __get_fpsr(fpsr);
-  fpu_control_t fpcr;
-  __get_fpcr(fpcr);
-  fenv_t env = { .__status = fpsr, .__control = fpcr };
-  *envp = env;
-
-  // Clear all exceptions.
-  fpsr &= ~FE_ALL_EXCEPT;
-  __set_fpsr(fpsr);
+  fegetenv(envp);
+  feclearexcept(FE_ALL_EXCEPT);
   return 0;
 }
 
 int feupdateenv(const fenv_t* envp) {
-  fpu_status_t fpsr;
-  fpu_control_t fpcr;
-
-  // Set FPU Control register.
-  __get_fpcr(fpcr);
-  if (envp->__control != fpcr) {
-    __set_fpcr(envp->__control);
-  }
-
-  // Set FPU Status register to status | currently raised exceptions.
-  __get_fpsr(fpsr);
-  fpsr = envp->__status | (fpsr & FE_ALL_EXCEPT);
-  __set_fpsr(fpsr);
+  int excepts = fetestexcept(FE_ALL_EXCEPT);
+  fesetenv(envp);
+  feraiseexcept(excepts);
   return 0;
 }
 
diff --git a/tests/fenv_test.cpp b/tests/fenv_test.cpp
index ad34caa..9cf9d98 100644
--- a/tests/fenv_test.cpp
+++ b/tests/fenv_test.cpp
@@ -202,9 +202,10 @@
 
 TEST(fenv, feenableexcept_fegetexcept) {
 #if !defined(ANDROID_HOST_MUSL)
-#if defined(__aarch64__) || defined(__arm__)
-  // ARM doesn't support this. They used to if you go back far enough, but it was removed in
-  // the Cortex-A8 between r3p1 and r3p2.
+#if defined(__aarch64__) || defined(__arm__) || defined(__riscv)
+  // ARM and RISC-V don't support hardware trapping of floating point
+  // exceptions. ARM used to if you go back far enough, but it was
+  // removed in the Cortex-A8 between r3p1 and r3p2. RISC-V never has.
   ASSERT_EQ(-1, feenableexcept(FE_INVALID));
   ASSERT_EQ(0, fegetexcept());
   ASSERT_EQ(-1, feenableexcept(FE_DIVBYZERO));
@@ -215,8 +216,10 @@
   ASSERT_EQ(0, fegetexcept());
   ASSERT_EQ(-1, feenableexcept(FE_INEXACT));
   ASSERT_EQ(0, fegetexcept());
+#if defined(_FE_DENORMAL)  // riscv64 doesn't support this.
   ASSERT_EQ(-1, feenableexcept(FE_DENORMAL));
   ASSERT_EQ(0, fegetexcept());
+#endif
 #else
   // We can't recover from SIGFPE, so sacrifice a child...
   pid_t pid = fork();