Merge "bionic: arm64: generic: strcmp: align to 64B cache line"
am: f785a6cbff

Change-Id: I3b5b76a6c9a0881c9f82012161254dbd480d062b
diff --git a/libc/arch-arm64/generic/bionic/strcmp.S b/libc/arch-arm64/generic/bionic/strcmp.S
index 3cce478..271452d 100644
--- a/libc/arch-arm64/generic/bionic/strcmp.S
+++ b/libc/arch-arm64/generic/bionic/strcmp.S
@@ -57,6 +57,7 @@
 
 	/* Start of performance-critical section  -- one 64B cache line.  */
 ENTRY(strcmp)
+.p2align  6
 	eor	tmp1, src1, src2
 	mov	zeroones, #REP8_01
 	tst	tmp1, #7