Update to v5.11 kernel headers.
Kernel headers coming from:
Git: https://android.googlesource.com/kernel/common/
Branch: android-mainline
Tag: android-mainline-5.11
Test: Built cuttlefish and flame images. Ran bionic unit tests on both.
Change-Id: Ie60337aafad4bda55af99b6c8fe9f56bf2fa787f
diff --git a/libc/kernel/uapi/linux/pci_regs.h b/libc/kernel/uapi/linux/pci_regs.h
index 19a6fb6..81450a7 100644
--- a/libc/kernel/uapi/linux/pci_regs.h
+++ b/libc/kernel/uapi/linux/pci_regs.h
@@ -440,6 +440,7 @@
#define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003
#define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004
#define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005
+#define PCI_EXP_LNKCAP_SLS_64_0GB 0x00000006
#define PCI_EXP_LNKCAP_MLW 0x000003f0
#define PCI_EXP_LNKCAP_ASPMS 0x00000c00
#define PCI_EXP_LNKCAP_ASPM_L0S 0x00000400
@@ -471,6 +472,7 @@
#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003
#define PCI_EXP_LNKSTA_CLS_16_0GB 0x0004
#define PCI_EXP_LNKSTA_CLS_32_0GB 0x0005
+#define PCI_EXP_LNKSTA_CLS_64_0GB 0x0006
#define PCI_EXP_LNKSTA_NLW 0x03f0
#define PCI_EXP_LNKSTA_NLW_X1 0x0010
#define PCI_EXP_LNKSTA_NLW_X2 0x0020
@@ -571,6 +573,7 @@
#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008
#define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010
#define PCI_EXP_LNKCAP2_SLS_32_0GB 0x00000020
+#define PCI_EXP_LNKCAP2_SLS_64_0GB 0x00000040
#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100
#define PCI_EXP_LNKCTL2 48
#define PCI_EXP_LNKCTL2_TLS 0x000f
@@ -579,6 +582,7 @@
#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003
#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004
#define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005
+#define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006
#define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010
#define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380
#define PCI_EXP_LNKCTL2_HASD 0x0020
@@ -621,6 +625,7 @@
#define PCI_EXT_CAP_ID_DPC 0x1D
#define PCI_EXT_CAP_ID_L1SS 0x1E
#define PCI_EXT_CAP_ID_PTM 0x1F
+#define PCI_EXT_CAP_ID_DVSEC 0x23
#define PCI_EXT_CAP_ID_DLF 0x25
#define PCI_EXT_CAP_ID_PL_16GT 0x26
#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT
@@ -718,6 +723,11 @@
#define PCI_PWR_CAP 12
#define PCI_PWR_CAP_BUDGET(x) ((x) & 1)
#define PCI_EXT_CAP_PWR_SIZEOF 16
+#define PCI_RCEC_RCIEP_BITMAP 4
+#define PCI_RCEC_BUSN 8
+#define PCI_RCEC_BUSN_REG_VER 0x02
+#define PCI_RCEC_BUSN_NEXT(x) (((x) >> 8) & 0xff)
+#define PCI_RCEC_BUSN_LAST(x) (((x) >> 16) & 0xff)
#define PCI_VNDR_HEADER 4
#define PCI_VNDR_HEADER_ID(x) ((x) & 0xffff)
#define PCI_VNDR_HEADER_REV(x) (((x) >> 16) & 0xf)
@@ -909,6 +919,8 @@
#define PCI_L1SS_CTL1_LTR_L12_TH_VALUE 0x03ff0000
#define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000
#define PCI_L1SS_CTL2 0x0c
+#define PCI_DVSEC_HEADER1 0x4
+#define PCI_DVSEC_HEADER2 0x8
#define PCI_DLF_CAP 0x04
#define PCI_DLF_EXCHANGE_ENABLE 0x80000000
#define PCI_PL_16GT_LE_CTRL 0x20