diff --git a/tests/fenv_test.cpp b/tests/fenv_test.cpp
index ad34caa..9cf9d98 100644
--- a/tests/fenv_test.cpp
+++ b/tests/fenv_test.cpp
@@ -202,9 +202,10 @@
 
 TEST(fenv, feenableexcept_fegetexcept) {
 #if !defined(ANDROID_HOST_MUSL)
-#if defined(__aarch64__) || defined(__arm__)
-  // ARM doesn't support this. They used to if you go back far enough, but it was removed in
-  // the Cortex-A8 between r3p1 and r3p2.
+#if defined(__aarch64__) || defined(__arm__) || defined(__riscv)
+  // ARM and RISC-V don't support hardware trapping of floating point
+  // exceptions. ARM used to if you go back far enough, but it was
+  // removed in the Cortex-A8 between r3p1 and r3p2. RISC-V never has.
   ASSERT_EQ(-1, feenableexcept(FE_INVALID));
   ASSERT_EQ(0, fegetexcept());
   ASSERT_EQ(-1, feenableexcept(FE_DIVBYZERO));
@@ -215,8 +216,10 @@
   ASSERT_EQ(0, fegetexcept());
   ASSERT_EQ(-1, feenableexcept(FE_INEXACT));
   ASSERT_EQ(0, fegetexcept());
+#if defined(_FE_DENORMAL)  // riscv64 doesn't support this.
   ASSERT_EQ(-1, feenableexcept(FE_DENORMAL));
   ASSERT_EQ(0, fegetexcept());
+#endif
 #else
   // We can't recover from SIGFPE, so sacrifice a child...
   pid_t pid = fork();